From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id BBF0B19A0A for ; Thu, 20 Jul 2023 12:50:58 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1689857458; x=1721393458; h=message-id:date:mime-version:cc:subject:to:references: from:in-reply-to:content-transfer-encoding; bh=0AeQWKZgQumjGRyu50VkLRMKLVhVKVhQS0rXychQk0w=; b=CbUGEQBEMIb1r2tdw2fpKmnPoaDmHVDzCVZhrNiDW1f0pe1OjPlNjDX/ cgcVRtw76FVclUe5KBopKku3RcwXZqSbPRNbxzMSOjOCz+amI0IVhdMNx JSY0NYsr3E549V15o8AJgIpWoyIZpVearo4uSfbaQiQ+TJ3o1BzsxgKXz UcyRZ9bAJkWk9rFve6h2eNwHqei+qyTamMdmIwePLVNsjh5cCOGQOvfLc 2NP1xrRE7Cxwpef5Y8d2sXmQ/GtMLMfLM/bn9sYCqvIM8xSPtDqra4y1m 5N3oZavI5NdmsCNhAU19EhGCzq2ZVyPIq8b1kv7lrBUC9Nof2bCuvcIDG w==; X-IronPort-AV: E=McAfee;i="6600,9927,10776"; a="453091717" X-IronPort-AV: E=Sophos;i="6.01,218,1684825200"; d="scan'208";a="453091717" Received: from orsmga004.jf.intel.com ([10.7.209.38]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 20 Jul 2023 05:50:55 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10776"; a="848436243" X-IronPort-AV: E=Sophos;i="6.01,218,1684825200"; d="scan'208";a="848436243" Received: from blu2-mobl.ccr.corp.intel.com (HELO [10.252.191.109]) ([10.252.191.109]) by orsmga004-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 20 Jul 2023 05:50:48 -0700 Message-ID: <2556751a-c439-bb69-a102-583dd985fc5e@linux.intel.com> Date: Thu, 20 Jul 2023 20:50:43 +0800 Precedence: bulk X-Mailing-List: iommu@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:102.0) Gecko/20100101 Thunderbird/102.13.0 Cc: baolu.lu@linux.intel.com, Palmer Dabbelt , Albert Ou , Anup Patel , Sunil V L , Nick Kossifidis , Sebastien Boeuf , iommu@lists.linux.dev, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux@rivosinc.com Subject: Re: [PATCH 05/11] RISC-V: drivers/iommu/riscv: Add sysfs interface Content-Language: en-US To: Tomasz Jeznach , Joerg Roedel , Will Deacon , Robin Murphy , Paul Walmsley References: <610abe685f90870be52bc7c2ca45ab5235bd8eb4.1689792825.git.tjeznach@rivosinc.com> From: Baolu Lu In-Reply-To: <610abe685f90870be52bc7c2ca45ab5235bd8eb4.1689792825.git.tjeznach@rivosinc.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit On 2023/7/20 3:33, Tomasz Jeznach wrote: > +#define sysfs_dev_to_iommu(dev) \ > + container_of(dev_get_drvdata(dev), struct riscv_iommu_device, iommu) > + > +static ssize_t address_show(struct device *dev, > + struct device_attribute *attr, char *buf) > +{ > + struct riscv_iommu_device *iommu = sysfs_dev_to_iommu(dev); > + return sprintf(buf, "%llx\n", iommu->reg_phys); Use sysfs_emit() please. > +} > + > +static DEVICE_ATTR_RO(address); > + > +#define ATTR_RD_REG32(name, offset) \ > + ssize_t reg_ ## name ## _show(struct device *dev, \ > + struct device_attribute *attr, char *buf) \ > +{ \ > + struct riscv_iommu_device *iommu = sysfs_dev_to_iommu(dev); \ > + return sprintf(buf, "0x%x\n", \ > + riscv_iommu_readl(iommu, offset)); \ > +} > + > +#define ATTR_RD_REG64(name, offset) \ > + ssize_t reg_ ## name ## _show(struct device *dev, \ > + struct device_attribute *attr, char *buf) \ > +{ \ > + struct riscv_iommu_device *iommu = sysfs_dev_to_iommu(dev); \ > + return sprintf(buf, "0x%llx\n", \ > + riscv_iommu_readq(iommu, offset)); \ > +} > + > +#define ATTR_WR_REG32(name, offset) \ > + ssize_t reg_ ## name ## _store(struct device *dev, \ > + struct device_attribute *attr, \ > + const char *buf, size_t len) \ > +{ \ > + struct riscv_iommu_device *iommu = sysfs_dev_to_iommu(dev); \ > + unsigned long val; \ > + int ret; \ > + ret = kstrtoul(buf, 0, &val); \ > + if (ret) \ > + return ret; \ > + riscv_iommu_writel(iommu, offset, val); \ > + return len; \ > +} > + > +#define ATTR_WR_REG64(name, offset) \ > + ssize_t reg_ ## name ## _store(struct device *dev, \ > + struct device_attribute *attr, \ > + const char *buf, size_t len) \ > +{ \ > + struct riscv_iommu_device *iommu = sysfs_dev_to_iommu(dev); \ > + unsigned long long val; \ > + int ret; \ > + ret = kstrtoull(buf, 0, &val); \ > + if (ret) \ > + return ret; \ > + riscv_iommu_writeq(iommu, offset, val); \ > + return len; \ > +} So this allows users to change the registers through sysfs? How does it synchronize with the iommu driver? Best regards, baolu