iommu.lists.linux-foundation.org archive mirror
 help / color / mirror / Atom feed
From: Robin Murphy <robin.murphy@arm.com>
To: Sebastian Ott <sebott@amazon.de>, Joerg Roedel <joro@8bytes.org>
Cc: Benjamin Serebrin <serebrin@amazon.com>,
	Filippo Sironi <sironi@amazon.de>,
	iommu@lists.linux-foundation.org
Subject: Re: [PATCH v2 0/3] iommu/amd: I/O VA address limits
Date: Fri, 17 Jul 2020 10:47:13 +0100	[thread overview]
Message-ID: <271d67b2-482e-7a16-8fd7-1f1a6a4bdff2@arm.com> (raw)
In-Reply-To: <751e403f-7095-f761-465b-9e187b423b0b@amazon.de>

On 2020-07-17 10:20, Sebastian Ott via iommu wrote:
> Hello Joerg,
> 
> On 2020-07-10 14:31, Joerg Roedel wrote:
>> On Wed, Jul 01, 2020 at 12:46:31AM +0200, Sebastian Ott wrote:
>>> The IVRS ACPI table specifies maximum address sizes for I/O virtual
>>> addresses that can be handled by the IOMMUs in the system. Parse that
>>> data from the IVRS header to provide aperture information for DMA
>>> mappings and users of the iommu API.
>>>
>>> Changes for V2:
>>>   - use limits in iommu_setup_dma_ops()
>>>   - rebased to current upstream
>>>
>>> Sebastian Ott (3):
>>>    iommu/amd: Parse supported address sizes from IVRS
>>>    iommu/amd: Restrict aperture for domains to conform with IVRS
>>>    iommu/amd: Actually enforce geometry aperture
>> Thanks for the changes. May I ask what the reason for those changes are?
>> AFAIK all AMD IOMMU implementations (in hardware) support full 64bit
>> address spaces, and the IVRS table might actually be wrong, limiting the
>> address space in the worst case to only 32 bit.
> 
> It's not the IOMMU, but we've encountered devices that are capable of 
> more than
> 32- but less than 64- bit IOVA, and there's no way to express that to 
> the IOVA
> allocator in the PCIe spec. Our solution was to have our platforms 
> express an
> IVRS entry that says the IOMMU is capable of 48-bit, which these devices 
> can generate.
> 48 bits is plenty of address space in this generation for the 
> application we have.

Hmm, for constraints of individual devices, it should really be their 
drivers' job to call dma_set_mask*() with the appropriate value in the 
first place rather than just assuming that 64 means anything >32. If 
it's a case where the device itself technically is 64-bit capable, but 
an upstream bridge is constraining it, then that limit can also be 
described either by dedicated firmware properties (e.g. ACPI _DMA) or 
with a quirk like via_no_dac().

Robin.
_______________________________________________
iommu mailing list
iommu@lists.linux-foundation.org
https://lists.linuxfoundation.org/mailman/listinfo/iommu

  reply	other threads:[~2020-07-17  9:47 UTC|newest]

Thread overview: 19+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-06-05 14:56 [PATCH 0/3] iommu/amd: I/O VA address limits Sebastian Ott via iommu
2020-06-05 14:56 ` [PATCH 1/3] iommu/amd: Parse supported address sizes from IVRS Sebastian Ott via iommu
2020-06-05 14:56 ` [PATCH 2/3] iommu/amd: Restrict aperture for domains to conform with IVRS Sebastian Ott via iommu
2020-06-05 14:56 ` [PATCH 3/3] iommu/amd: Actually enforce geometry aperture Sebastian Ott via iommu
2020-06-30  9:30   ` Joerg Roedel
2020-06-30 22:46     ` [PATCH v2 0/3] iommu/amd: I/O VA address limits Sebastian Ott via iommu
2020-06-30 22:46       ` [PATCH v2 1/3] iommu/amd: Parse supported address sizes from IVRS Sebastian Ott via iommu
2020-06-30 22:46       ` [PATCH v2 2/3] iommu/amd: Restrict aperture for domains to conform with IVRS Sebastian Ott via iommu
2020-06-30 22:46       ` [PATCH v2 3/3] iommu/amd: Actually enforce geometry aperture Sebastian Ott via iommu
2020-07-10 12:31       ` [PATCH v2 0/3] iommu/amd: I/O VA address limits Joerg Roedel
2020-07-17  9:20         ` Sebastian Ott via iommu
2020-07-17  9:47           ` Robin Murphy [this message]
2020-07-17 13:22             ` Sironi, Filippo via iommu
2020-07-17 14:36               ` Robin Murphy
2020-07-17 15:15                 ` Sironi, Filippo via iommu
2020-07-22 12:19                   ` joro
2020-07-22 12:34                     ` Sironi, Filippo via iommu
2020-07-22 14:00                       ` joro
2020-06-24 16:09 ` [PATCH " Sebastian Ott via iommu

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=271d67b2-482e-7a16-8fd7-1f1a6a4bdff2@arm.com \
    --to=robin.murphy@arm.com \
    --cc=iommu@lists.linux-foundation.org \
    --cc=joro@8bytes.org \
    --cc=sebott@amazon.de \
    --cc=serebrin@amazon.com \
    --cc=sironi@amazon.de \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).