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Tue, 06 Jun 2023 08:07:02 +0000 Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA01.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 3568708N006720 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 6 Jun 2023 08:07:00 GMT Received: from [10.214.66.58] (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.42; Tue, 6 Jun 2023 01:06:53 -0700 Message-ID: <327b8d8a-edc9-f0a6-6c7d-070b8bb86ed5@quicinc.com> Date: Tue, 6 Jun 2023 13:36:50 +0530 Precedence: bulk X-Mailing-List: iommu@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:91.0) Gecko/20100101 Thunderbird/91.6.0 Subject: Re: [PATCH v2 08/10] arm64: dts: qcom: Add QUPv3 UART console node for SDX75 Content-Language: en-US To: Konrad Dybcio , , , , , , , , , , , , , , CC: , , , , , References: <1685982557-28326-1-git-send-email-quic_rohiagar@quicinc.com> <1685982557-28326-9-git-send-email-quic_rohiagar@quicinc.com> From: Rohit Agarwal In-Reply-To: Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 7bit X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: G2z3kGFlJJ1RCZNoTkUurkFP1dv2JYQV X-Proofpoint-GUID: G2z3kGFlJJ1RCZNoTkUurkFP1dv2JYQV X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.957,Hydra:6.0.573,FMLib:17.11.176.26 definitions=2023-06-06_04,2023-06-05_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 bulkscore=0 adultscore=0 priorityscore=1501 malwarescore=0 impostorscore=0 lowpriorityscore=0 suspectscore=0 spamscore=0 clxscore=1015 mlxscore=0 mlxlogscore=999 phishscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2304280000 definitions=main-2306060069 On 6/5/2023 11:47 PM, Konrad Dybcio wrote: > > On 5.06.2023 18:29, Rohit Agarwal wrote: >> Add the debug uart console node in devicetree. >> >> Signed-off-by: Rohit Agarwal >> --- >> arch/arm64/boot/dts/qcom/sdx75.dtsi | 49 +++++++++++++++++++++++++++++++++++++ >> 1 file changed, 49 insertions(+) >> >> diff --git a/arch/arm64/boot/dts/qcom/sdx75.dtsi b/arch/arm64/boot/dts/qcom/sdx75.dtsi >> index f83eef8..47170ae 100644 >> --- a/arch/arm64/boot/dts/qcom/sdx75.dtsi >> +++ b/arch/arm64/boot/dts/qcom/sdx75.dtsi >> @@ -385,6 +385,34 @@ >> #power-domain-cells = <1>; >> }; >> >> + qupv3_id_0: geniqup@9c0000 { >> + compatible = "qcom,geni-se-qup"; >> + reg = <0x0 0x009c0000 0x0 0x2000>; >> + clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, >> + <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; >> + clock-names = "m-ahb", >> + "s-ahb"; >> + iommus = <&apps_smmu 0xe3 0x0>; >> + #address-cells = <2>; >> + #size-cells = <2>; >> + ranges; >> + status = "disabled"; >> + >> + uart1: serial@984000 { >> + compatible = "qcom,geni-debug-uart"; >> + reg = <0x0 0x00984000 0x0 0x4000>; >> + clock-names = "se"; >> + clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; >> + interrupts = ; >> + pinctrl-0 = <&qupv3_se1_2uart_tx_active>, >> + <&qupv3_se1_2uart_rx_active>; >> + pinctrl-1 = <&qupv3_se1_2uart_sleep>; >> + pinctrl-names = "default", >> + "sleep"; >> + status = "disabled"; >> + }; >> + }; >> + >> tcsr_mutex: hwlock@1f40000 { >> compatible = "qcom,tcsr-mutex"; >> reg = <0x0 0x01f40000 0x0 0x40000>; >> @@ -413,6 +441,27 @@ >> interrupt-controller; >> #interrupt-cells = <2>; >> wakeup-parent = <&pdc>; >> + >> + qupv3_se1_2uart_tx_active: qupv3-se1-2uart-tx-active-state { >> + pins = "gpio12"; >> + function = "qup_se1_l2_mira"; >> + drive-strength= <2>; >> + bias-disable; >> + }; > You can bunch these two up like this: > > qupv3_se1_2uart_active: qup.... { > tx { > pins = ... > foo = ... > }; > > rx { > pins = ... > bar = ... > }; > }; Sure will do this in the next version having all this in the single patch. Thanks, Rohit. > Konrad >> + >> + qupv3_se1_2uart_rx_active: qupv3-se1-2uart-rx-active-state { >> + pins = "gpio13"; >> + function = "qup_se1_l3_mira"; >> + drive-strength= <2>; >> + bias-disable; >> + }; >> + >> + qupv3_se1_2uart_sleep: qupv3-se1-2uart-sleep-state { >> + pins = "gpio12", "gpio13"; >> + function = "gpio"; >> + drive-strength = <2>; >> + bias-pull-down; >> + }; >> }; >> >> apps_smmu: iommu@15000000 {