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Sun, 25 Oct 2020 09:49:03 +0000 From: David Laight To: 'David Woodhouse' , "x86@kernel.org" Subject: RE: [PATCH v3 17/35] x86/pci/xen: Use msi_msg shadow structs Thread-Topic: [PATCH v3 17/35] x86/pci/xen: Use msi_msg shadow structs Thread-Index: AQHWqk3aux8nicxw2kqi6TJIJCakiamoEtJw Date: Sun, 25 Oct 2020 09:49:03 +0000 Message-ID: <3e69326016524d97bcdea35d0765cc68@AcuMS.aculab.com> References: <20201024213535.443185-1-dwmw2@infradead.org> <20201024213535.443185-18-dwmw2@infradead.org> In-Reply-To: <20201024213535.443185-18-dwmw2@infradead.org> Accept-Language: en-GB, en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-ms-exchange-transport-fromentityheader: Hosted x-originating-ip: [10.202.205.107] MIME-Version: 1.0 Authentication-Results: relay.mimecast.com; auth=pass smtp.auth=C51A453 smtp.mailfrom=david.laight@aculab.com X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: aculab.com Content-Language: en-US Cc: "linux-hyperv@vger.kernel.org" , kvm , Dexuan Cui , linux-kernel , "iommu@lists.linux-foundation.org" , "maz@misterjones.org" , Paolo Bonzini , Thomas Gleixner X-BeenThere: iommu@lists.linux-foundation.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: Development issues for Linux IOMMU support List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Errors-To: iommu-bounces@lists.linux-foundation.org Sender: "iommu" From: David Woodhouse > Sent: 24 October 2020 22:35 > > From: Thomas Gleixner > > Use the msi_msg shadow structs and compose the message with named bitfields > instead of the unreadable macro maze. > > Signed-off-by: Thomas Gleixner > Signed-off-by: David Woodhouse > --- > arch/x86/pci/xen.c | 26 +++++++++++--------------- > 1 file changed, 11 insertions(+), 15 deletions(-) > > diff --git a/arch/x86/pci/xen.c b/arch/x86/pci/xen.c > index c552cd2d0632..3d41a09c2c14 100644 > --- a/arch/x86/pci/xen.c > +++ b/arch/x86/pci/xen.c > @@ -152,7 +152,6 @@ static int acpi_register_gsi_xen(struct device *dev, u32 gsi, > > #if defined(CONFIG_PCI_MSI) > #include > -#include > > struct xen_pci_frontend_ops *xen_pci_frontend; > EXPORT_SYMBOL_GPL(xen_pci_frontend); > @@ -210,23 +209,20 @@ static int xen_setup_msi_irqs(struct pci_dev *dev, int nvec, int type) > return ret; > } > > -#define XEN_PIRQ_MSI_DATA (MSI_DATA_TRIGGER_EDGE | \ > - MSI_DATA_LEVEL_ASSERT | (3 << 8) | MSI_DATA_VECTOR(0)) > - > static void xen_msi_compose_msg(struct pci_dev *pdev, unsigned int pirq, > struct msi_msg *msg) > { > - /* We set vector == 0 to tell the hypervisor we don't care about it, > - * but we want a pirq setup instead. > - * We use the dest_id field to pass the pirq that we want. */ > - msg->address_hi = MSI_ADDR_BASE_HI | MSI_ADDR_EXT_DEST_ID(pirq); > - msg->address_lo = > - MSI_ADDR_BASE_LO | > - MSI_ADDR_DEST_MODE_PHYSICAL | > - MSI_ADDR_REDIRECTION_CPU | > - MSI_ADDR_DEST_ID(pirq); > - > - msg->data = XEN_PIRQ_MSI_DATA; > + /* > + * We set vector == 0 to tell the hypervisor we don't care about > + * it, but we want a pirq setup instead. We use the dest_id fields > + * to pass the pirq that we want. > + */ > + memset(msg, 0, sizeof(*msg)); > + msg->address_hi = X86_MSI_BASE_ADDRESS_HIGH; > + msg->arch_addr_hi.destid_8_31 = pirq >> 8; > + msg->arch_addr_lo.destid_0_7 = pirq & 0xFF; > + msg->arch_addr_lo.base_address = X86_MSI_BASE_ADDRESS_LOW; > + msg->arch_data.delivery_mode = APIC_DELIVERY_MODE_EXTINT; > } Just looking at a random one of these patches... Does the compiler manage to optimise that reasonably? Or does it generate a lot of shifts and masks as each bitfield is set? The code generation for bitfields is often a lot worse that that for |= setting bits in a word. David - Registered Address Lakeside, Bramley Road, Mount Farm, Milton Keynes, MK1 1PT, UK Registration No: 1397386 (Wales) _______________________________________________ iommu mailing list iommu@lists.linux-foundation.org https://lists.linuxfoundation.org/mailman/listinfo/iommu