From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 01E0A1855 for ; Wed, 26 Jul 2023 03:21:49 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1690341710; x=1721877710; h=message-id:date:mime-version:cc:subject:to:references: from:in-reply-to:content-transfer-encoding; bh=41wbTtODPkpjnhNbDqWe3jLLGDqh9EzgVAF8fhApyhM=; b=alNNBDxRj6IDMbD0KVj5Vt0pn5gJPz9FA8uXRRLSRCe19mRss+w89JXK NYA4u3lYw040DEhSjlYjrFXEk0pcB13j3vtw39BsDYx6j2dUSHGJ6iN6M iN5Vpv4xgdJq+ZnBTevZxzK+vlduT3dJEr3EpXvm+Ae0gc76Bu5J7ayK+ WQzuycpdG3hjLii6i2X0d7duGg6BTnhr5fLWNQo/VTEZ+wHdjYdskmCDx qF3YFNWwJpbV5F9y22GO/dicPtnd/1GPEXiAjWxpOp8cY3pgembW6+zFf a1ZjophyA1TSO3j0blV0+Qjhcv1l7hO3H8+8L4zpiCxi8FOqjmtaBZcCY w==; X-IronPort-AV: E=McAfee;i="6600,9927,10782"; a="371513239" X-IronPort-AV: E=Sophos;i="6.01,231,1684825200"; d="scan'208";a="371513239" Received: from orsmga002.jf.intel.com ([10.7.209.21]) by orsmga103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 25 Jul 2023 20:21:40 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10782"; a="726345744" X-IronPort-AV: E=Sophos;i="6.01,231,1684825200"; d="scan'208";a="726345744" Received: from blu2-mobl.ccr.corp.intel.com (HELO [10.254.208.129]) ([10.254.208.129]) by orsmga002-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 25 Jul 2023 20:21:36 -0700 Message-ID: <592edb17-7fa4-3b5b-2803-e8c50c322eee@linux.intel.com> Date: Wed, 26 Jul 2023 11:21:34 +0800 Precedence: bulk X-Mailing-List: iommu@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:102.0) Gecko/20100101 Thunderbird/102.13.0 Cc: baolu.lu@linux.intel.com, Tomasz Jeznach , Joerg Roedel , Will Deacon , Robin Murphy , Paul Walmsley , Albert Ou , linux@rivosinc.com, linux-kernel@vger.kernel.org, Sebastien Boeuf , iommu@lists.linux.dev, Palmer Dabbelt , Nick Kossifidis , linux-riscv@lists.infradead.org Subject: Re: [PATCH 03/11] dt-bindings: Add RISC-V IOMMU bindings To: Zong Li , Anup Patel References: Content-Language: en-US From: Baolu Lu In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit On 2023/7/24 21:23, Zong Li wrote: >>>>> In RISC-V IOMMU, certain devices can be set to bypass mode when the >>>>> IOMMU is in translation mode. To identify the devices that require >>>>> bypass mode by default, does it be sensible to add a property to >>>>> indicate this behavior? >>>> Bypass mode for a device is a property of that device (similar to dma-coherent) >>>> and not of the IOMMU. Other architectures (ARM and x86) never added such >>>> a device property for bypass mode so I guess it is NOT ADVISABLE to do it. >>>> >>>> If this is REALLY required then we can do something similar to the QCOM >>>> SMMU driver where they have a whitelist of devices which are allowed to >>>> be in bypass mode (i.e. IOMMU_DOMAIN_IDENTITY) based their device >>>> compatible string and any device outside this whitelist is blocked by default. >>>> >>> I have considered that adding the property of bypass mode to that >>> device would be more appropriate. However, if we want to define this >>> property for the device, it might need to go through the generic IOMMU >>> dt-bindings, but I'm not sure if other IOMMU devices need this. I am >>> bringing up this topic here because I would like to explore if there >>> are any solutions on the IOMMU side, such as a property that indicates >>> the phandle of devices wishing to set bypass mode, somewhat similar to >>> the whitelist you mentioned earlier. Do you think we should address >>> this? After all, this is a case of RISC-V IOMMU supported. >> Bypass mode is a common feature across IOMMUs. Other IOMMUs don't >> have a special property for bypass mode at device-level or at IOMMU level, >> which clearly indicates that defining a RISC-V specific property is not the >> right way to go. >> >> The real question is how do we set IOMMU_DOMAIN_IDENTITY (i.e. >> bypass/identity domain) as the default domain for certain devices ? >> >> One possible option is to implement def_domain_type() IOMMU operation >> for RISC-V IOMMU which will return IOMMU_DOMAIN_IDENTITY for >> certain devices based on compatible string matching (i.e. whitelist of >> devices). As an example, refer qcom_smmu_def_domain_type() >> of drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c >> > That is indeed one way to approach it, and we can modify the > compatible string when we want to change the mode. However, it would > be preferable to explore a more flexible approach to achieve this > goal. By doing so, we can avoid hard coding anything in the driver or > having to rebuild the kernel whenever we want to change the mode for > certain devices. While I have considered extending a cell in the > 'iommus' property to indicate a device's desire to set bypass mode, it > doesn't comply with the iommu documentation and could lead to > ambiguous definitions. Hard coding the matching strings in the iommu driver is definitely not a preferable way. A feasible solution from current code's point of view is that platform opt-in the device's special requirements through DT or ACPI. And in the def_domain_type callback, let the iommu core know that, hence it can allocate a right type of domain for the device. Thoughts? Best regards, baolu