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From: Steven Price <steven.price@arm.com>
To: Robin Murphy <robin.murphy@arm.com>, will@kernel.org, joro@8bytes.org
Cc: robh@kernel.org, iommu@lists.linux-foundation.org,
	linux-arm-kernel@lists.infradead.org, tomeu.vizoso@collabora.com,
	narmstrong@baylibre.com
Subject: Re: [PATCH 2/3] iommu/io-pgtable-arm: Support more Mali configurations
Date: Thu, 12 Sep 2019 11:47:49 +0100
Message-ID: <6e3f7b2f-fa84-422f-602a-0773835018cb@arm.com> (raw)
In-Reply-To: <69c934789ad2bf486b03682563ea2262ea6d9301.1568211045.git.robin.murphy@arm.com>

On 11/09/2019 15:42, Robin Murphy wrote:
> In principle, Midgard GPUs supporting smaller VA sizes should only
> require 3-level pagetables, since the address bits resolved at level 0
> (47:40) will never change. However, the kbase driver does not appear to
> have any notion of a variable start level, and empirically T720 and T820
> rapidly blow up with translation faults unless given a full 4-level
> table, despite only supporting a 33-bit VA size.

Midgard 'LPAE' isn't really LPAE and does indeed always require all
levels of page tables. The 33-bit VA size is really only limiting the
storage of virtual addresses in the GPU and not affecting the MMU.

> The 'real' IAS value is still valuable in terms of validating addresses
> on map/unmap, so tweak the allocator to allow smaller values while still
> forcing the resultant tables to the full 4 levels.
> 
> Signed-off-by: Robin Murphy <robin.murphy@arm.com>

Reviewed-by: Steven Price <steven.price@arm.com>

Steve

> ---
>  drivers/iommu/io-pgtable-arm.c | 7 ++++++-
>  1 file changed, 6 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/iommu/io-pgtable-arm.c b/drivers/iommu/io-pgtable-arm.c
> index 9e35cd991f06..77f41c9dd9be 100644
> --- a/drivers/iommu/io-pgtable-arm.c
> +++ b/drivers/iommu/io-pgtable-arm.c
> @@ -1022,7 +1022,7 @@ arm_mali_lpae_alloc_pgtable(struct io_pgtable_cfg *cfg, void *cookie)
>  	if (cfg->quirks)
>  		return NULL;
>  
> -	if (cfg->ias != 48 || cfg->oas > 40)
> +	if (cfg->ias > 48 || cfg->oas > 40)
>  		return NULL;
>  
>  	cfg->pgsize_bitmap &= (SZ_4K | SZ_2M | SZ_1G);
> @@ -1031,6 +1031,11 @@ arm_mali_lpae_alloc_pgtable(struct io_pgtable_cfg *cfg, void *cookie)
>  	if (!data)
>  		return NULL;
>  
> +	/* Mali seems to need a full 4-level table regardless of IAS */
> +	if (data->levels < ARM_LPAE_MAX_LEVELS) {
> +		data->levels = ARM_LPAE_MAX_LEVELS;
> +		data->pgd_size = sizeof(arm_lpae_iopte);
> +	}
>  	/*
>  	 * MEMATTR: Mali has no actual notion of a non-cacheable type, so the
>  	 * best we can do is mimic the out-of-tree driver and hope that the
> 

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Thread overview: 13+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-09-11 14:42 [PATCH 0/3] iommu/io-pgtable-arm: Mali LPAE improvements Robin Murphy
2019-09-11 14:42 ` [PATCH 1/3] iommu/io-pgtable-arm: Correct Mali attributes Robin Murphy
2019-09-12 10:41   ` Steven Price
2019-09-11 14:42 ` [PATCH 2/3] iommu/io-pgtable-arm: Support more Mali configurations Robin Murphy
2019-09-12 10:47   ` Steven Price [this message]
2019-09-11 14:42 ` [PATCH 3/3] iommu/io-pgtable-arm: Allow coherent walks for Mali Robin Murphy
2019-09-12 10:53   ` Steven Price
2019-09-11 16:19 ` [PATCH 0/3] iommu/io-pgtable-arm: Mali LPAE improvements Neil Armstrong
2019-09-11 16:20   ` Will Deacon
2019-09-11 17:19     ` Robin Murphy
2019-09-19  8:30       ` Will Deacon
2019-09-23  8:17         ` Tomeu Vizoso
2019-09-23 11:04           ` Robin Murphy

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