From: Sebastian Ott via iommu <iommu@lists.linux-foundation.org>
To: Joerg Roedel <joro@8bytes.org>
Cc: Benjamin Serebrin <serebrin@amazon.com>,
Filippo Sironi <sironi@amazon.de>,
iommu@lists.linux-foundation.org
Subject: Re: [PATCH v2 0/3] iommu/amd: I/O VA address limits
Date: Fri, 17 Jul 2020 11:20:58 +0200 [thread overview]
Message-ID: <751e403f-7095-f761-465b-9e187b423b0b@amazon.de> (raw)
In-Reply-To: <20200710123059.GF27672@8bytes.org>
Hello Joerg,
On 2020-07-10 14:31, Joerg Roedel wrote:
> On Wed, Jul 01, 2020 at 12:46:31AM +0200, Sebastian Ott wrote:
>> The IVRS ACPI table specifies maximum address sizes for I/O virtual
>> addresses that can be handled by the IOMMUs in the system. Parse that
>> data from the IVRS header to provide aperture information for DMA
>> mappings and users of the iommu API.
>>
>> Changes for V2:
>> - use limits in iommu_setup_dma_ops()
>> - rebased to current upstream
>>
>> Sebastian Ott (3):
>> iommu/amd: Parse supported address sizes from IVRS
>> iommu/amd: Restrict aperture for domains to conform with IVRS
>> iommu/amd: Actually enforce geometry aperture
> Thanks for the changes. May I ask what the reason for those changes are?
> AFAIK all AMD IOMMU implementations (in hardware) support full 64bit
> address spaces, and the IVRS table might actually be wrong, limiting the
> address space in the worst case to only 32 bit.
It's not the IOMMU, but we've encountered devices that are capable of
more than
32- but less than 64- bit IOVA, and there's no way to express that to
the IOVA
allocator in the PCIe spec. Our solution was to have our platforms
express an
IVRS entry that says the IOMMU is capable of 48-bit, which these devices
can generate.
48 bits is plenty of address space in this generation for the
application we have.
Sebastian
Amazon Development Center Germany GmbH
Krausenstr. 38
10117 Berlin
Geschaeftsfuehrung: Christian Schlaeger, Jonathan Weiss
Eingetragen am Amtsgericht Charlottenburg unter HRB 149173 B
Sitz: Berlin
Ust-ID: DE 289 237 879
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next prev parent reply other threads:[~2020-07-17 9:21 UTC|newest]
Thread overview: 19+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-06-05 14:56 [PATCH 0/3] iommu/amd: I/O VA address limits Sebastian Ott via iommu
2020-06-05 14:56 ` [PATCH 1/3] iommu/amd: Parse supported address sizes from IVRS Sebastian Ott via iommu
2020-06-05 14:56 ` [PATCH 2/3] iommu/amd: Restrict aperture for domains to conform with IVRS Sebastian Ott via iommu
2020-06-05 14:56 ` [PATCH 3/3] iommu/amd: Actually enforce geometry aperture Sebastian Ott via iommu
2020-06-30 9:30 ` Joerg Roedel
2020-06-30 22:46 ` [PATCH v2 0/3] iommu/amd: I/O VA address limits Sebastian Ott via iommu
2020-06-30 22:46 ` [PATCH v2 1/3] iommu/amd: Parse supported address sizes from IVRS Sebastian Ott via iommu
2020-06-30 22:46 ` [PATCH v2 2/3] iommu/amd: Restrict aperture for domains to conform with IVRS Sebastian Ott via iommu
2020-06-30 22:46 ` [PATCH v2 3/3] iommu/amd: Actually enforce geometry aperture Sebastian Ott via iommu
2020-07-10 12:31 ` [PATCH v2 0/3] iommu/amd: I/O VA address limits Joerg Roedel
2020-07-17 9:20 ` Sebastian Ott via iommu [this message]
2020-07-17 9:47 ` Robin Murphy
2020-07-17 13:22 ` Sironi, Filippo via iommu
2020-07-17 14:36 ` Robin Murphy
2020-07-17 15:15 ` Sironi, Filippo via iommu
2020-07-22 12:19 ` joro
2020-07-22 12:34 ` Sironi, Filippo via iommu
2020-07-22 14:00 ` joro
2020-06-24 16:09 ` [PATCH " Sebastian Ott via iommu
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