From: Robin Murphy <robin.murphy@arm.com>
To: Tomasz Nowicki <tn@semihalf.com>,
will@kernel.org, joro@8bytes.org, gregory.clement@bootlin.com,
robh+dt@kernel.org, hannah@marvell.com
Cc: devicetree@vger.kernel.org, catalin.marinas@arm.com,
linux-kernel@vger.kernel.org, nadavh@marvell.com,
iommu@lists.linux-foundation.org, mw@semihalf.com,
linux-arm-kernel@lists.infradead.org
Subject: Re: [PATCH v4 2/4] iommu/arm-smmu: Workaround for Marvell Armada-AP806 SoC erratum #582743
Date: Wed, 15 Jul 2020 11:32:30 +0100 [thread overview]
Message-ID: <793ede4d-79e9-3615-9da1-57cfe1a44c4d@arm.com> (raw)
In-Reply-To: <20200715070649.18733-3-tn@semihalf.com>
On 2020-07-15 08:06, Tomasz Nowicki wrote:
> From: Hanna Hawa <hannah@marvell.com>
>
> Due to erratum #582743, the Marvell Armada-AP806 can't access 64bit to
> ARM SMMUv2 registers.
>
> Provide implementation relevant hooks:
> - split the writeq/readq to two accesses of writel/readl.
> - mask the MMU_IDR2.PTFSv8 fields to not use AArch64 format (but
> only AARCH32_L) since with AArch64 format 32 bits access is not supported.
>
> Note that most 64-bit registers like TTBRn can be accessed as two 32-bit
> halves without issue, and AArch32 format ensures that the register writes
> which must be atomic (for TLBI etc.) need only be 32-bit.
Thanks Tomasz, this has ended up as clean as I'd hoped it could, and
there's still room to come back and play more complicated games later if
a real need for AARCH64_64K at stage 2 crops up.
Reviewed-by: Robin Murphy <robin.murphy@arm.com>
> Signed-off-by: Hanna Hawa <hannah@marvell.com>
> Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
> Signed-off-by: Tomasz Nowicki <tn@semihalf.com>
> ---
> Documentation/arm64/silicon-errata.rst | 3 ++
> drivers/iommu/arm-smmu-impl.c | 45 ++++++++++++++++++++++++++
> 2 files changed, 48 insertions(+)
>
> diff --git a/Documentation/arm64/silicon-errata.rst b/Documentation/arm64/silicon-errata.rst
> index 936cf2a59ca4..157214d3abe1 100644
> --- a/Documentation/arm64/silicon-errata.rst
> +++ b/Documentation/arm64/silicon-errata.rst
> @@ -125,6 +125,9 @@ stable kernels.
> | Cavium | ThunderX2 Core | #219 | CAVIUM_TX2_ERRATUM_219 |
> +----------------+-----------------+-----------------+-----------------------------+
> +----------------+-----------------+-----------------+-----------------------------+
> +| Marvell | ARM-MMU-500 | #582743 | N/A |
> ++----------------+-----------------+-----------------+-----------------------------+
> ++----------------+-----------------+-----------------+-----------------------------+
And in case anyone feels like nit-picking the order here, I think the
current respective corporate structures perfectly justify "Marvell"
sorting alphabetically before "NXP", to be next to "Cavium" :D
Robin.
> | Freescale/NXP | LS2080A/LS1043A | A-008585 | FSL_ERRATUM_A008585 |
> +----------------+-----------------+-----------------+-----------------------------+
> +----------------+-----------------+-----------------+-----------------------------+
> diff --git a/drivers/iommu/arm-smmu-impl.c b/drivers/iommu/arm-smmu-impl.c
> index c75b9d957b70..59422cb92488 100644
> --- a/drivers/iommu/arm-smmu-impl.c
> +++ b/drivers/iommu/arm-smmu-impl.c
> @@ -147,6 +147,48 @@ static const struct arm_smmu_impl arm_mmu500_impl = {
> .reset = arm_mmu500_reset,
> };
>
> +static u64 mrvl_mmu500_readq(struct arm_smmu_device *smmu, int page, int off)
> +{
> + /*
> + * Marvell Armada-AP806 erratum #582743.
> + * Split all the readq to double readl
> + */
> + return hi_lo_readq_relaxed(arm_smmu_page(smmu, page) + off);
> +}
> +
> +static void mrvl_mmu500_writeq(struct arm_smmu_device *smmu, int page, int off,
> + u64 val)
> +{
> + /*
> + * Marvell Armada-AP806 erratum #582743.
> + * Split all the writeq to double writel
> + */
> + hi_lo_writeq_relaxed(val, arm_smmu_page(smmu, page) + off);
> +}
> +
> +static int mrvl_mmu500_cfg_probe(struct arm_smmu_device *smmu)
> +{
> +
> + /*
> + * Armada-AP806 erratum #582743.
> + * Hide the SMMU_IDR2.PTFSv8 fields to sidestep the AArch64
> + * formats altogether and allow using 32 bits access on the
> + * interconnect.
> + */
> + smmu->features &= ~(ARM_SMMU_FEAT_FMT_AARCH64_4K |
> + ARM_SMMU_FEAT_FMT_AARCH64_16K |
> + ARM_SMMU_FEAT_FMT_AARCH64_64K);
> +
> + return 0;
> +}
> +
> +static const struct arm_smmu_impl mrvl_mmu500_impl = {
> + .read_reg64 = mrvl_mmu500_readq,
> + .write_reg64 = mrvl_mmu500_writeq,
> + .cfg_probe = mrvl_mmu500_cfg_probe,
> + .reset = arm_mmu500_reset,
> +};
> +
>
> struct arm_smmu_device *arm_smmu_impl_init(struct arm_smmu_device *smmu)
> {
> @@ -175,5 +217,8 @@ struct arm_smmu_device *arm_smmu_impl_init(struct arm_smmu_device *smmu)
> of_device_is_compatible(np, "qcom,sc7180-smmu-500"))
> return qcom_smmu_impl_init(smmu);
>
> + if (of_device_is_compatible(np, "marvell,ap806-smmu-500"))
> + smmu->impl = &mrvl_mmu500_impl;
> +
> return smmu;
> }
>
_______________________________________________
iommu mailing list
iommu@lists.linux-foundation.org
https://lists.linuxfoundation.org/mailman/listinfo/iommu
next prev parent reply other threads:[~2020-07-15 10:32 UTC|newest]
Thread overview: 23+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-07-15 7:06 [PATCH v4 0/4] Add system mmu support for Armada-806 Tomasz Nowicki
2020-07-15 7:06 ` [PATCH v4 1/4] iommu/arm-smmu: Call configuration impl hook before consuming features Tomasz Nowicki
2020-07-15 10:20 ` Robin Murphy
2020-07-15 7:06 ` [PATCH v4 2/4] iommu/arm-smmu: Workaround for Marvell Armada-AP806 SoC erratum #582743 Tomasz Nowicki
2020-07-15 10:32 ` Robin Murphy [this message]
2020-07-16 7:24 ` Tomasz Nowicki
2020-07-15 7:06 ` [PATCH v4 3/4] dt-bindings: arm-smmu: add compatible string for Marvell Armada-AP806 SMMU-500 Tomasz Nowicki
2020-07-15 10:36 ` Robin Murphy
2020-07-16 7:27 ` Tomasz Nowicki
2020-07-15 7:06 ` [PATCH v4 4/4] arm64: dts: marvell: add SMMU support Tomasz Nowicki
2020-07-18 21:08 ` Gregory CLEMENT
2020-07-16 12:00 ` [PATCH v4 0/4] Add system mmu support for Armada-806 Will Deacon
2020-07-16 12:02 ` Will Deacon
2020-07-16 12:49 ` Marcin Wojtas
2020-07-18 21:07 ` Gregory CLEMENT
2020-10-06 15:16 ` Denis Odintsov
2020-10-07 13:55 ` Marcin Wojtas
2020-10-13 13:08 ` Robin Murphy
2020-10-19 11:41 ` Denis Odintsov
2020-10-23 12:19 ` Tomasz Nowicki
2020-10-23 12:33 ` Robin Murphy
2020-10-23 13:05 ` Tomasz Nowicki
2020-10-23 13:26 ` Denis Odintsov
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=793ede4d-79e9-3615-9da1-57cfe1a44c4d@arm.com \
--to=robin.murphy@arm.com \
--cc=catalin.marinas@arm.com \
--cc=devicetree@vger.kernel.org \
--cc=gregory.clement@bootlin.com \
--cc=hannah@marvell.com \
--cc=iommu@lists.linux-foundation.org \
--cc=joro@8bytes.org \
--cc=linux-arm-kernel@lists.infradead.org \
--cc=linux-kernel@vger.kernel.org \
--cc=mw@semihalf.com \
--cc=nadavh@marvell.com \
--cc=robh+dt@kernel.org \
--cc=tn@semihalf.com \
--cc=will@kernel.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).