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dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=none smtp.mailfrom=vivek.gautam@codeaurora.org Subject: Re: [PATCH v2 17/17] iommu/arm-smmu: Add context init implementation hook To: Robin Murphy , will@kernel.org References: From: Vivek Gautam Message-ID: <8306f3f1-925c-0b02-8103-9d4a510005b2@codeaurora.org> Date: Tue, 20 Aug 2019 15:45:20 +0530 User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:60.0) Gecko/20100101 Thunderbird/60.8.0 MIME-Version: 1.0 In-Reply-To: Content-Type: multipart/mixed; boundary="------------80B028CDD5943A54CA33F4D2" Content-Language: en-US Cc: gregory.clement@bootlin.com, bjorn.andersson@linaro.org, iommu@lists.linux-foundation.org, linux-arm-kernel@lists.infradead.org X-BeenThere: iommu@lists.linux-foundation.org X-Mailman-Version: 2.1.12 Precedence: list List-Id: Development issues for Linux IOMMU support List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: iommu-bounces@lists.linux-foundation.org Errors-To: iommu-bounces@lists.linux-foundation.org This is a multi-part message in MIME format. --------------80B028CDD5943A54CA33F4D2 Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 7bit On 8/16/2019 12:07 AM, Robin Murphy wrote: > Allocating and initialising a context for a domain is another point > where certain implementations are known to want special behaviour. > Currently the other half of the Cavium workaround comes into play here, > so let's finish the job to get the whole thing right out of the way. > > Signed-off-by: Robin Murphy > --- > drivers/iommu/arm-smmu-impl.c | 42 ++++++++++++++++++++++++++--- > drivers/iommu/arm-smmu.c | 51 +++++++---------------------------- > drivers/iommu/arm-smmu.h | 42 +++++++++++++++++++++++++++-- > 3 files changed, 87 insertions(+), 48 deletions(-) > > diff --git a/drivers/iommu/arm-smmu-impl.c b/drivers/iommu/arm-smmu-impl.c > index 4dc8b1c4befb..e22e9004f449 100644 > --- a/drivers/iommu/arm-smmu-impl.c > +++ b/drivers/iommu/arm-smmu-impl.c > @@ -48,25 +48,60 @@ const struct arm_smmu_impl calxeda_impl = { > }; > > > +struct cavium_smmu { > + struct arm_smmu_device smmu; > + u32 id_base; > +}; > + > static int cavium_cfg_probe(struct arm_smmu_device *smmu) > { > static atomic_t context_count = ATOMIC_INIT(0); > + struct cavium_smmu *cs = container_of(smmu, struct cavium_smmu, smmu); > /* > * Cavium CN88xx erratum #27704. > * Ensure ASID and VMID allocation is unique across all SMMUs in > * the system. > */ > - smmu->cavium_id_base = atomic_fetch_add(smmu->num_context_banks, > - &context_count); > + cs->id_base = atomic_fetch_add(smmu->num_context_banks, &context_count); > dev_notice(smmu->dev, "\tenabling workaround for Cavium erratum 27704\n"); > > return 0; > } > > +int cavium_init_context(struct arm_smmu_domain *smmu_domain) > +{ > + struct cavium_smmu *cs = container_of(smmu_domain->smmu, > + struct cavium_smmu, smmu); > + > + if (smmu_domain->stage == ARM_SMMU_DOMAIN_S2) > + smmu_domain->cfg.vmid += cs->id_base; > + else > + smmu_domain->cfg.asid += cs->id_base; > + > + return 0; > +} > + > const struct arm_smmu_impl cavium_impl = { > .cfg_probe = cavium_cfg_probe, > + .init_context = cavium_init_context, > }; > > +struct arm_smmu_device *cavium_smmu_impl_init(struct arm_smmu_device *smmu) > +{ > + struct cavium_smmu *cs; > + > + cs = devm_kzalloc(smmu->dev, sizeof(*cs), GFP_KERNEL); > + if (!cs) > + return ERR_PTR(-ENOMEM); > + > + cs->smmu = *smmu; > + cs->smmu.impl = &cavium_impl; > + > + devm_kfree(smmu->dev, smmu); > + > + return &cs->smmu; > +} > + > > #define ARM_MMU500_ACTLR_CPRE (1 << 1) > > @@ -126,8 +161,7 @@ struct arm_smmu_device *arm_smmu_impl_init(struct arm_smmu_device *smmu) > smmu->impl = &arm_mmu500_impl; > break; > case CAVIUM_SMMUV2: > - smmu->impl = &cavium_impl; > - break; > + return cavium_smmu_impl_init(smmu); > default: > break; > } > diff --git a/drivers/iommu/arm-smmu.c b/drivers/iommu/arm-smmu.c > index fc98992d120d..b8628e2ab579 100644 > --- a/drivers/iommu/arm-smmu.c > +++ b/drivers/iommu/arm-smmu.c > @@ -27,7 +27,6 @@ > #include > #include > #include > -#include > #include > #include > #include > @@ -111,44 +110,6 @@ struct arm_smmu_master_cfg { > #define for_each_cfg_sme(fw, i, idx) \ > for (i = 0; idx = fwspec_smendx(fw, i), i < fw->num_ids; ++i) > > -enum arm_smmu_context_fmt { > - ARM_SMMU_CTX_FMT_NONE, > - ARM_SMMU_CTX_FMT_AARCH64, > - ARM_SMMU_CTX_FMT_AARCH32_L, > - ARM_SMMU_CTX_FMT_AARCH32_S, > -}; > - > -struct arm_smmu_cfg { > - u8 cbndx; > - u8 irptndx; > - union { > - u16 asid; > - u16 vmid; > - }; > - enum arm_smmu_cbar_type cbar; > - enum arm_smmu_context_fmt fmt; > -}; > -#define INVALID_IRPTNDX 0xff > - > -enum arm_smmu_domain_stage { > - ARM_SMMU_DOMAIN_S1 = 0, > - ARM_SMMU_DOMAIN_S2, > - ARM_SMMU_DOMAIN_NESTED, > - ARM_SMMU_DOMAIN_BYPASS, > -}; > - > -struct arm_smmu_domain { > - struct arm_smmu_device *smmu; > - struct io_pgtable_ops *pgtbl_ops; > - const struct iommu_gather_ops *tlb_ops; > - struct arm_smmu_cfg cfg; > - enum arm_smmu_domain_stage stage; > - bool non_strict; > - struct mutex init_mutex; /* Protects smmu pointer */ > - spinlock_t cb_lock; /* Serialises ATS1* ops and TLB syncs */ > - struct iommu_domain domain; > -}; > - > static bool using_legacy_binding, using_generic_binding; > > static inline int arm_smmu_rpm_get(struct arm_smmu_device *smmu) > @@ -749,9 +710,16 @@ static int arm_smmu_init_domain_context(struct iommu_domain *domain, > } > > if (smmu_domain->stage == ARM_SMMU_DOMAIN_S2) > - cfg->vmid = cfg->cbndx + 1 + smmu->cavium_id_base; > + cfg->vmid = cfg->cbndx + 1; > else > - cfg->asid = cfg->cbndx + smmu->cavium_id_base; > + cfg->asid = cfg->cbndx; > + > + smmu_domain->smmu = smmu; > + if (smmu->impl && smmu->impl->init_context) { > + ret = smmu->impl->init_context(smmu_domain); > + if (ret) > + goto out_unlock; > + } > > pgtbl_cfg = (struct io_pgtable_cfg) { > .pgsize_bitmap = smmu->pgsize_bitmap, > @@ -765,7 +733,6 @@ static int arm_smmu_init_domain_context(struct iommu_domain *domain, > if (smmu_domain->non_strict) > pgtbl_cfg.quirks |= IO_PGTABLE_QUIRK_NON_STRICT; > > - smmu_domain->smmu = smmu; > pgtbl_ops = alloc_io_pgtable_ops(fmt, &pgtbl_cfg, smmu_domain); > if (!pgtbl_ops) { > ret = -ENOMEM; > diff --git a/drivers/iommu/arm-smmu.h b/drivers/iommu/arm-smmu.h > index ddafe872a396..611ed742e56f 100644 > --- a/drivers/iommu/arm-smmu.h > +++ b/drivers/iommu/arm-smmu.h > @@ -14,6 +14,7 @@ > #include > #include > #include > +#include > #include > #include > #include > @@ -270,14 +271,50 @@ struct arm_smmu_device { > struct clk_bulk_data *clks; > int num_clks; > > - u32 cavium_id_base; /* Specific to Cavium */ > - > spinlock_t global_sync_lock; > > /* IOMMU core code handle */ > struct iommu_device iommu; > }; > > +enum arm_smmu_context_fmt { > + ARM_SMMU_CTX_FMT_NONE, > + ARM_SMMU_CTX_FMT_AARCH64, > + ARM_SMMU_CTX_FMT_AARCH32_L, > + ARM_SMMU_CTX_FMT_AARCH32_S, > +}; > + > +struct arm_smmu_cfg { > + u8 cbndx; > + u8 irptndx; > + union { > + u16 asid; > + u16 vmid; > + }; > + enum arm_smmu_cbar_type cbar; > + enum arm_smmu_context_fmt fmt; > +}; > +#define INVALID_IRPTNDX 0xff > + > +enum arm_smmu_domain_stage { > + ARM_SMMU_DOMAIN_S1 = 0, > + ARM_SMMU_DOMAIN_S2, > + ARM_SMMU_DOMAIN_NESTED, > + ARM_SMMU_DOMAIN_BYPASS, > +}; > + > +struct arm_smmu_domain { > + struct arm_smmu_device *smmu; > + struct io_pgtable_ops *pgtbl_ops; > + const struct iommu_gather_ops *tlb_ops; > + struct arm_smmu_cfg cfg; > + enum arm_smmu_domain_stage stage; > + bool non_strict; > + struct mutex init_mutex; /* Protects smmu pointer */ > + spinlock_t cb_lock; /* Serialises ATS1* ops and TLB syncs */ > + struct iommu_domain domain; > +}; > + > > /* Implementation details, yay! */ > struct arm_smmu_impl { > @@ -289,6 +326,7 @@ struct arm_smmu_impl { > u64 val); > int (*cfg_probe)(struct arm_smmu_device *smmu); > int (*reset)(struct arm_smmu_device *smmu); > + int (*init_context)(struct arm_smmu_domain *smmu_domain); Hi Robin, Sorry for responding late to this series. I have couple of doubts here that I wanted to discuss. Are we standardizing these implementation specific ops? Each vendor implementations will have something peculiar to take care. Things are good right now with 'reset', 'cfg_probe', and 'init_context' hooks. But, on top of vendor implementation details, there can be SoC specific errata changes that need to be added. Moreover, adding implementation data based on __model__ may not suffice for long. Do you suggest adding any other data variable in the ARM_SMMU_MATCH_DATA? To show SoC specific needs, I have the change attached in this email to take care of the SDM845 'wait-for-safe' sequence. Please take a look. Thanks & Regards Vivek > }; > > static inline void __iomem *arm_smmu_page(struct arm_smmu_device *smmu, int n) --------------80B028CDD5943A54CA33F4D2 Content-Type: text/plain; charset=UTF-8; name="0003-iommu-arm-smmu-impl-Add-SDM845-specific-implementati.patch" Content-Transfer-Encoding: base64 Content-Disposition: attachment; filename*0="0003-iommu-arm-smmu-impl-Add-SDM845-specific-implementati.pa"; filename*1="tch" RnJvbSAzODMwZWM3ZTIyZGViNDlkZTcyYjZiYzI5YmQ5NjVmN2IwN2I5NjY5IE1vbiBTZXAg MTcgMDA6MDA6MDAgMjAwMQpGcm9tOiBWaXZlayBHYXV0YW0gPHZpdmVrLmdhdXRhbUBjb2Rl YXVyb3JhLm9yZz4KRGF0ZTogVHVlLCAyMCBBdWcgMjAxOSAxNToyODoxNiArMDUzMApTdWJq ZWN0OiBbUEFUQ0ggMy80XSBpb21tdTogYXJtLXNtbXUtaW1wbDogQWRkIFNETTg0NSBzcGVj aWZpYyBpbXBsZW1lbnRhdGlvbgogaG9vawoKU2lnbmVkLW9mZi1ieTogVml2ZWsgR2F1dGFt IDx2aXZlay5nYXV0YW1AY29kZWF1cm9yYS5vcmc+Ci0tLQogZHJpdmVycy9pb21tdS9hcm0t c21tdS1pbXBsLmMgfCAzMSArKysrKysrKysrKysrKysrKysrKysrKysrKysrKysrCiBkcml2 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