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From: Auger Eric <eric.auger@redhat.com>
To: Jacob Pan <jacob.jun.pan@linux.intel.com>,
	iommu@lists.linux-foundation.org,
	LKML <linux-kernel@vger.kernel.org>,
	Lu Baolu <baolu.lu@linux.intel.com>,
	Joerg Roedel <joro@8bytes.org>,
	David Woodhouse <dwmw2@infradead.org>
Cc: "Tian, Kevin" <kevin.tian@intel.com>, Raj Ashok <ashok.raj@intel.com>
Subject: Re: [PATCH v4 4/7] iommu/vt-d: Handle non-page aligned address
Date: Thu, 16 Jul 2020 09:51:54 +0200	[thread overview]
Message-ID: <889b3fcd-482a-46b7-7b95-19555f73f907@redhat.com> (raw)
In-Reply-To: <1594080774-33413-5-git-send-email-jacob.jun.pan@linux.intel.com>

Hi Jacob,

On 7/7/20 2:12 AM, Jacob Pan wrote:
> From: Liu Yi L <yi.l.liu@intel.com>
> 
> Address information for device TLB invalidation comes from userspace
> when device is directly assigned to a guest with vIOMMU support.
> VT-d requires page aligned address. This patch checks and enforce
> address to be page aligned, otherwise reserved bits can be set in the
> invalidation descriptor. Unrecoverable fault will be reported due to
> non-zero value in the reserved bits.
> 
> Fixes: 61a06a16e36d8 ("iommu/vt-d: Support flushing more translation
> cache types")
> Acked-by: Lu Baolu <baolu.lu@linux.intel.com>
> Signed-off-by: Liu Yi L <yi.l.liu@intel.com>
> Signed-off-by: Jacob Pan <jacob.jun.pan@linux.intel.com>
Reviewed-by: Eric Auger <eric.auger@redhat.com>

Thanks

Eric
> 
> ---
>  drivers/iommu/intel/dmar.c | 20 ++++++++++++++++++--
>  1 file changed, 18 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/iommu/intel/dmar.c b/drivers/iommu/intel/dmar.c
> index d9f973fa1190..b2c53bada905 100644
> --- a/drivers/iommu/intel/dmar.c
> +++ b/drivers/iommu/intel/dmar.c
> @@ -1455,9 +1455,25 @@ void qi_flush_dev_iotlb_pasid(struct intel_iommu *iommu, u16 sid, u16 pfsid,
>  	 * Max Invs Pending (MIP) is set to 0 for now until we have DIT in
>  	 * ECAP.
>  	 */
> -	desc.qw1 |= addr & ~mask;
> -	if (size_order)
> +	if (addr & GENMASK_ULL(size_order + VTD_PAGE_SHIFT, 0))
> +		pr_warn_ratelimited("Invalidate non-aligned address %llx, order %d\n", addr, size_order);
> +
> +	/* Take page address */
> +	desc.qw1 = QI_DEV_EIOTLB_ADDR(addr);
> +
> +	if (size_order) {
> +		/*
> +		 * Existing 0s in address below size_order may be the least
> +		 * significant bit, we must set them to 1s to avoid having
> +		 * smaller size than desired.
> +		 */
> +		desc.qw1 |= GENMASK_ULL(size_order + VTD_PAGE_SHIFT,
> +					VTD_PAGE_SHIFT);
> +		/* Clear size_order bit to indicate size */
> +		desc.qw1 &= ~mask;
> +		/* Set the S bit to indicate flushing more than 1 page */
>  		desc.qw1 |= QI_DEV_EIOTLB_SIZE;
> +	}
>  
>  	qi_submit_sync(iommu, &desc, 1, 0);
>  }
> 

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  parent reply	other threads:[~2020-07-16  7:52 UTC|newest]

Thread overview: 16+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-07-07  0:12 [PATCH v4 0/7] iommu/vt-d: Misc tweaks and fixes for vSVA Jacob Pan
2020-07-07  0:12 ` [PATCH v4 1/7] iommu/vt-d: Enforce PASID devTLB field mask Jacob Pan
2020-07-07  0:12 ` [PATCH v4 2/7] iommu/vt-d: Remove global page support in devTLB flush Jacob Pan
2020-07-07  0:12 ` [PATCH v4 3/7] iommu/vt-d: Fix PASID devTLB invalidation Jacob Pan
2020-07-16  7:52   ` Auger Eric
2020-07-07  0:12 ` [PATCH v4 4/7] iommu/vt-d: Handle non-page aligned address Jacob Pan
2020-07-07 13:32   ` kernel test robot
2020-07-09  1:10     ` [kbuild-all] " Li, Philip
2020-07-16  7:51   ` Auger Eric [this message]
2020-07-21 16:50   ` Jacob Pan
2020-07-22  1:01     ` Lu Baolu
2020-07-22 18:20       ` Jacob Pan
2020-07-07  0:12 ` [PATCH v4 5/7] iommu/vt-d: Fix devTLB flush for vSVA Jacob Pan
2020-07-07  0:12 ` [PATCH v4 6/7] iommu/vt-d: Warn on out-of-range invalidation address Jacob Pan
2020-07-16  8:40   ` Auger Eric
2020-07-07  0:12 ` [PATCH v4 7/7] iommu/vt-d: Disable multiple GPASID-dev bind Jacob Pan

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