From: Robin Murphy <robin.murphy@arm.com>
To: Rob Herring <robh@kernel.org>,
Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Cc: Tomeu Vizoso <tomeu.vizoso@collabora.com>,
Neil Armstrong <narmstrong@baylibre.com>,
Kevin Hilman <khilman@baylibre.com>,
dri-devel <dri-devel@lists.freedesktop.org>,
Steven Price <steven.price@arm.com>,
Linux IOMMU <iommu@lists.linux-foundation.org>,
"open list:ARM/Amlogic Meson..."
<linux-amlogic@lists.infradead.org>,
Will Deacon <will@kernel.org>,
linux-arm-kernel <linux-arm-kernel@lists.infradead.org>,
Jerome Brunet <jbrunet@baylibre.com>
Subject: Re: [PATCH 0/3] drm: panfrost: Coherency support
Date: Thu, 17 Sep 2020 13:38:16 +0100 [thread overview]
Message-ID: <88bc6b29-9206-477f-4c45-a1e55efb66af@arm.com> (raw)
In-Reply-To: <CAL_JsqLGO4YYPjQsjnzZCW5iT6n+keZw9G9mFALJip0nDo42Hw@mail.gmail.com>
On 2020-09-16 18:46, Rob Herring wrote:
> On Wed, Sep 16, 2020 at 11:04 AM Alyssa Rosenzweig
> <alyssa.rosenzweig@collabora.com> wrote:
>>
>>> So I get a performance regression with the dma-coherent approach, even if it's
>>> clearly the cleaner.
>>
>> That's bizarre -- this should really be the faster of the two.
>
> Coherency may not be free. CortexA9 had something like 4x slower
> memcpy if SMP was enabled as an example. I don't know if there's
> anything going on like that specifically here. If there's never any
> CPU accesses mixed in with kmscube, then there would be no benefit to
> coherency.
There will still be CPU benefits in terms of not having to spend time
cache-cleaning every BO upon allocation, and less overhead on writing
out descriptors in the first place (due to cacheable vs. non-cacheable).
I haven't tried the NSh hack on Juno, but I don't see any notable
performance issue as-is - kmscube hits a solid 60FPS from the off (now
that it works without spewing faults). Given that the hardware on Juno
can be generously described as "less good", it would certainly be
interesting to figure out what difference is at play here...
The usual argument against I/O coherency is that it adds latency to
every access, but if you already have a coherent interconnect anyway
then the sensible answer to that is implementing decent snoop filters,
rather than making software more complicated.
Robin.
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prev parent reply other threads:[~2020-09-17 12:38 UTC|newest]
Thread overview: 22+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-09-15 23:51 [PATCH 0/3] drm: panfrost: Coherency support Robin Murphy
2020-09-15 23:51 ` [PATCH 1/3] iommu/io-pgtable-arm: Support coherency for Mali LPAE Robin Murphy
2020-09-21 17:57 ` Will Deacon
2020-09-21 21:53 ` Robin Murphy
2020-09-21 22:24 ` Will Deacon
2020-09-15 23:51 ` [PATCH 2/3] drm/panfrost: Support cache-coherent integrations Robin Murphy
2020-09-17 10:37 ` Steven Price
2020-09-15 23:51 ` [PATCH 3/3] arm64: dts: meson: Describe G12b GPU as coherent Robin Murphy
2020-09-16 8:26 ` Neil Armstrong
2020-10-05 8:15 ` Boris Brezillon
2020-10-05 8:34 ` Steven Price
2020-10-05 8:39 ` Boris Brezillon
2020-10-05 10:05 ` Steven Price
2020-09-16 14:54 ` Neil Armstrong
2020-09-16 14:54 ` [PATCH 0/3] drm: panfrost: Coherency support Neil Armstrong
2020-09-16 17:04 ` Alyssa Rosenzweig
2020-09-16 17:46 ` Rob Herring
2020-09-17 10:38 ` Steven Price
2020-09-17 10:51 ` Tomeu Vizoso
2020-09-17 11:00 ` Steven Price
2020-09-17 12:03 ` Alyssa Rosenzweig
2020-09-17 12:38 ` Robin Murphy [this message]
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