From: Lu Baolu <baolu.lu@linux.intel.com> To: Robin Murphy <robin.murphy@arm.com>, Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>, Joerg Roedel <joro@8bytes.org>, Tom Murphy <murphyt7@tcd.ie>, David Woodhouse <dwmw2@infradead.org>, Christoph Hellwig <hch@infradead.org> Cc: linux-kernel@vger.kernel.org, Intel-gfx@lists.freedesktop.org, Ashok Raj <ashok.raj@intel.com>, iommu@lists.linux-foundation.org Subject: Re: [PATCH v3 0/6] Convert the intel iommu driver to the dma-iommu api Date: Wed, 23 Sep 2020 13:38:05 +0800 [thread overview] Message-ID: <8d2a5124-92ce-2cdd-42a4-d7a22aa4e02a@linux.intel.com> (raw) In-Reply-To: <d4633137-136e-d96c-877a-b523018c51e7@arm.com> On 9/22/20 7:05 PM, Robin Murphy wrote: >>>> With the previous version of the series I hit a problem on Ivybridge >>>> where apparently the dma engine width is not respected. At least >>>> that is my layman interpretation of the errors. From the older thread: >>>> >>>> <3> [209.526605] DMAR: intel_iommu_map: iommu width (39) is not >>>> sufficient for the mapped address (ffff008000) >>>> >>>> Relevant iommu boot related messages are: >>>> >>>> <6>[ 0.184234] DMAR: Host address width 36 >>>> <6>[ 0.184245] DMAR: DRHD base: 0x000000fed90000 flags: 0x0 >>>> <6>[ 0.184288] DMAR: dmar0: reg_base_addr fed90000 ver 1:0 cap >>>> c0000020e60262 ecap f0101a >>>> <6>[ 0.184308] DMAR: DRHD base: 0x000000fed91000 flags: 0x1 >>>> <6>[ 0.184337] DMAR: dmar1: reg_base_addr fed91000 ver 1:0 cap >>>> c9008020660262 ecap f0105a >>>> <6>[ 0.184357] DMAR: RMRR base: 0x000000d8d28000 end: >>>> 0x000000d8d46fff >>>> <6>[ 0.184377] DMAR: RMRR base: 0x000000db000000 end: >>>> 0x000000df1fffff >>>> <6>[ 0.184398] DMAR-IR: IOAPIC id 2 under DRHD base 0xfed91000 >>>> IOMMU 1 >>>> <6>[ 0.184414] DMAR-IR: HPET id 0 under DRHD base 0xfed91000 >>>> <6>[ 0.184428] DMAR-IR: Queued invalidation will be enabled to >>>> support x2apic and Intr-remapping. >>>> <6>[ 0.185173] DMAR-IR: Enabled IRQ remapping in x2apic mode >>>> >>>> <6>[ 0.878934] DMAR: No ATSR found >>>> <6>[ 0.878966] DMAR: dmar0: Using Queued invalidation >>>> <6>[ 0.879007] DMAR: dmar1: Using Queued invalidation >>>> >>>> <6>[ 0.915032] DMAR: Intel(R) Virtualization Technology for >>>> Directed I/O >>>> <6>[ 0.915060] PCI-DMA: Using software bounce buffering for IO >>>> (SWIOTLB) >>>> <6>[ 0.915084] software IO TLB: mapped [mem >>>> 0xc80d4000-0xcc0d4000] (64MB) >>>> >>>> (Full boot log at >>>> https://intel-gfx-ci.01.org/tree/drm-tip/Trybot_7054/fi-ivb-3770/boot0.txt, >>>> failures at >>>> https://intel-gfx-ci.01.org/tree/drm-tip/Trybot_7054/fi-ivb-3770/igt@i915_selftest@live@blt.html.) >>>> >>>> >>>> Does this look familiar or at least plausible to you? Is this >>>> something your new series has fixed? >>> >>> This happens during attaching a domain to device. It has nothing to do >>> with this patch series. I will look into this issue, but not in this >>> email thread context. >> >> I am not sure what step is attaching domain to device, but these type >> messages: >> >> <3> [209.526605] DMAR: intel_iommu_map: iommu width (39) is not >> >> sufficient for the mapped address (ffff008000) >> >> They definitely appear to happen at runtime, as i915 is getting >> exercised by userspace. > > AFAICS this certainly might be related to this series - iommu-dma will Oh! I looked at the wrong function. prepare_domain_attach_device() prints a similar message which made me believe that it was not caused by the this patches series. > constrain IOVA allocation based on the domain geometry that the driver > reports, which in this case is set only once when first allocating the > domain. Thus it looks like both the dmar_domain->gaw adjustment in > prepare_domain_attach_device() and the domain_use_first_level() business > in intel_alloc_iova() effectively get lost in this conversion, since the > domain geometry never gets updated to reflect those additional constraints. Sounds reasonable. I will look into the code and work out a fix. > > Robin. > Best regards, baolu _______________________________________________ iommu mailing list iommu@lists.linux-foundation.org https://lists.linuxfoundation.org/mailman/listinfo/iommu
next prev parent reply other threads:[~2020-09-23 5:44 UTC|newest] Thread overview: 20+ messages / expand[flat|nested] mbox.gz Atom feed top 2020-09-12 3:21 Lu Baolu 2020-09-12 3:21 ` [PATCH v3 1/6] iommu: Handle freelists when using deferred flushing in iommu drivers Lu Baolu 2020-09-12 3:21 ` [PATCH v3 2/6] iommu: Add iommu_dma_free_cpu_cached_iovas() Lu Baolu 2020-09-12 3:21 ` [PATCH v3 3/6] iommu: Allow the dma-iommu api to use bounce buffers Lu Baolu 2020-09-12 3:21 ` [PATCH v3 4/6] iommu: Add quirk for Intel graphic devices in map_sg Lu Baolu 2020-09-12 3:21 ` [PATCH v3 5/6] iommu/vt-d: Convert intel iommu driver to the iommu ops Lu Baolu 2020-09-12 3:22 ` [PATCH v3 6/6] iommu/vt-d: Cleanup after converting to dma-iommu ops Lu Baolu 2020-09-14 8:04 ` [PATCH v3 0/6] Convert the intel iommu driver to the dma-iommu api Tvrtko Ursulin 2020-09-15 1:47 ` Lu Baolu 2020-09-15 8:31 ` Tvrtko Ursulin 2020-09-22 11:05 ` Robin Murphy 2020-09-23 5:38 ` Lu Baolu [this message] 2020-09-24 2:35 ` Lu Baolu 2020-09-18 20:47 ` [Intel-gfx] " Logan Gunthorpe 2020-09-20 6:36 ` Lu Baolu 2020-09-21 15:48 ` Logan Gunthorpe 2020-09-22 0:24 ` Lu Baolu 2020-09-22 15:38 ` Logan Gunthorpe 2020-09-22 9:51 ` Robin Murphy 2020-09-22 18:45 ` Logan Gunthorpe
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