From: Lu Baolu <baolu.lu@linux.intel.com>
To: Jacob Pan <jacob.jun.pan@linux.intel.com>,
LKML <linux-kernel@vger.kernel.org>,
iommu@lists.linux-foundation.org, Joerg Roedel <joro@8bytes.org>,
David Woodhouse <dwmw2@infradead.org>
Cc: "Tian, Kevin" <kevin.tian@intel.com>,
Raj Ashok <ashok.raj@intel.com>,
Sanjay Kumar <sanjay.k.kumar@intel.com>,
Jean-Philippe Brucker <jean-philippe@linaro.com>
Subject: Re: [PATCH v2 1/4] iommu/vt-d: Enable write protect for supervisor SVM
Date: Wed, 3 Mar 2021 12:56:37 +0800 [thread overview]
Message-ID: <9190a39d-13c2-c288-e8cd-a1c8adb8e600@linux.intel.com> (raw)
In-Reply-To: <1614680040-1989-2-git-send-email-jacob.jun.pan@linux.intel.com>
On 3/2/21 6:13 PM, Jacob Pan wrote:
> Write protect bit, when set, inhibits supervisor writes to the read-only
> pages. In supervisor shared virtual addressing (SVA), where page tables
> are shared between CPU and DMA, IOMMU PASID entry WPE bit should match
> CR0.WP bit in the CPU.
> This patch sets WPE bit for supervisor PASIDs if CR0.WP is set.
>
> Signed-off-by: Sanjay Kumar <sanjay.k.kumar@intel.com>
> Signed-off-by: Jacob Pan <jacob.jun.pan@linux.intel.com>
> ---
> drivers/iommu/intel/pasid.c | 26 ++++++++++++++++++++++++++
> 1 file changed, 26 insertions(+)
>
> diff --git a/drivers/iommu/intel/pasid.c b/drivers/iommu/intel/pasid.c
> index 0cceaabc3ce6..0b7e0e726ade 100644
> --- a/drivers/iommu/intel/pasid.c
> +++ b/drivers/iommu/intel/pasid.c
> @@ -410,6 +410,15 @@ static inline void pasid_set_sre(struct pasid_entry *pe)
> pasid_set_bits(&pe->val[2], 1 << 0, 1);
> }
>
> +/*
> + * Setup the WPE(Write Protect Enable) field (Bit 132) of a
> + * scalable mode PASID entry.
> + */
> +static inline void pasid_set_wpe(struct pasid_entry *pe)
> +{
> + pasid_set_bits(&pe->val[2], 1 << 4, 1 << 4);
> +}
> +
> /*
> * Setup the P(Present) field (Bit 0) of a scalable mode PASID
> * entry.
> @@ -553,6 +562,20 @@ static void pasid_flush_caches(struct intel_iommu *iommu,
> }
> }
>
> +static inline int pasid_enable_wpe(struct pasid_entry *pte)
> +{
> + unsigned long cr0 = read_cr0();
> +
> + /* CR0.WP is normally set but just to be sure */
> + if (unlikely(!(cr0 & X86_CR0_WP))) {
> + pr_err_ratelimited("No CPU write protect!\n");
> + return -EINVAL;
> + }
> + pasid_set_wpe(pte);
> +
> + return 0;
> +};
> +
> /*
> * Set up the scalable mode pasid table entry for first only
> * translation type.
> @@ -584,6 +607,9 @@ int intel_pasid_setup_first_level(struct intel_iommu *iommu,
> return -EINVAL;
> }
> pasid_set_sre(pte);
> + if (pasid_enable_wpe(pte))
> + return -EINVAL;
> +
> }
>
> if (flags & PASID_FLAG_FL5LP) {
>
Acked-by: Lu Baolu <baolu.lu@linux.intel.com>
Best regards,
baolu
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next prev parent reply other threads:[~2021-03-03 5:05 UTC|newest]
Thread overview: 11+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-03-02 10:13 [PATCH v2 0/4] Misc vSVA fixes for VT-d Jacob Pan
2021-03-02 10:13 ` [PATCH v2 1/4] iommu/vt-d: Enable write protect for supervisor SVM Jacob Pan
2021-03-03 4:56 ` Lu Baolu [this message]
2021-03-22 17:53 ` Guenter Roeck
2021-03-30 17:52 ` Jacob Pan
2021-03-30 19:02 ` Guenter Roeck
2021-03-02 10:13 ` [PATCH v2 2/4] iommu/vt-d: Enable write protect propagation from guest Jacob Pan
2021-03-03 4:57 ` Lu Baolu
2021-03-02 10:13 ` [PATCH v2 3/4] iommu/vt-d: Reject unsupported page request modes Jacob Pan
2021-03-02 10:14 ` [PATCH v2 4/4] iommu/vt-d: Calculate and set flags for handle_mm_fault Jacob Pan
2021-03-18 10:43 ` [PATCH v2 0/4] Misc vSVA fixes for VT-d Joerg Roedel
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