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Tue, 7 Apr 2020 02:43:27 -0700 Received: from shsmsx151.ccr.corp.intel.com (10.239.6.50) by FMSMSX125.amr.corp.intel.com (10.18.125.40) with Microsoft SMTP Server (TLS) id 14.3.439.0; Tue, 7 Apr 2020 02:43:27 -0700 Received: from shsmsx104.ccr.corp.intel.com ([169.254.5.225]) by SHSMSX151.ccr.corp.intel.com ([169.254.3.22]) with mapi id 14.03.0439.000; Tue, 7 Apr 2020 17:43:23 +0800 From: "Liu, Yi L" To: Jean-Philippe Brucker , Auger Eric Subject: RE: [PATCH v1 5/8] vfio/type1: Report 1st-level/stage-1 format to userspace Thread-Topic: [PATCH v1 5/8] vfio/type1: Report 1st-level/stage-1 format to userspace Thread-Index: AQHWAEUcqZEEdiOKbEGofjWp2Yic+6hjfq+AgAC/vLD//4YrAIAC1vWAgAbjh1A= Date: Tue, 7 Apr 2020 09:43:23 +0000 Message-ID: References: <1584880325-10561-1-git-send-email-yi.l.liu@intel.com> <1584880325-10561-6-git-send-email-yi.l.liu@intel.com> <20200403082305.GA1269501@myrica> In-Reply-To: <20200403082305.GA1269501@myrica> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: dlp-product: dlpe-windows dlp-version: 11.2.0.6 dlp-reaction: no-action x-originating-ip: [10.239.127.40] MIME-Version: 1.0 Cc: "Tian, Kevin" , "Raj, Ashok" , "kvm@vger.kernel.org" , "Tian, Jun J" , "Sun, Yi Y" , "linux-kernel@vger.kernel.org" , "alex.williamson@redhat.com" , "iommu@lists.linux-foundation.org" , "Wu, Hao" X-BeenThere: iommu@lists.linux-foundation.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: Development issues for Linux IOMMU support List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Errors-To: iommu-bounces@lists.linux-foundation.org Sender: "iommu" Hi Jean, > From: Jean-Philippe Brucker > Sent: Friday, April 3, 2020 4:23 PM > To: Auger Eric > userspace > > On Wed, Apr 01, 2020 at 03:01:12PM +0200, Auger Eric wrote: > > >>> header = vfio_info_cap_add(caps, sizeof(*nesting_cap), > > >>> VFIO_IOMMU_TYPE1_INFO_CAP_NESTING, 1); > @@ -2254,6 +2309,7 > > >>> @@ static int vfio_iommu_info_add_nesting_cap(struct > > >> vfio_iommu *iommu, > > >>> /* nesting iommu type supports PASID requests (alloc/free) */ > > >>> nesting_cap->nesting_capabilities |= VFIO_IOMMU_PASID_REQS; > > >> What is the meaning for ARM? > > > > > > I think it's just a software capability exposed to userspace, on > > > userspace side, it has a choice to use it or not. :-) The reason > > > define it and report it in cap nesting is that I'd like to make the > > > pasid alloc/free be available just for IOMMU with type > > > VFIO_IOMMU_TYPE1_NESTING. Please feel free tell me if it is not good > > > for ARM. We can find a proper way to report the availability. > > > > Well it is more a question for jean-Philippe. Do we have a system wide > > PASID allocation on ARM? > > We don't, the PASID spaces are per-VM on Arm, so this function should consult the > IOMMU driver before setting flags. As you said on patch 3, nested doesn't > necessarily imply PASID support. The SMMUv2 does not support PASID but does > support nesting stages 1 and 2 for the IOVA space. > SMMUv3 support of PASID depends on HW capabilities. So I think this needs to be > finer grained: > > Does the container support: > * VFIO_IOMMU_PASID_REQUEST? > -> Yes for VT-d 3 > -> No for Arm SMMU > * VFIO_IOMMU_{,UN}BIND_GUEST_PGTBL? > -> Yes for VT-d 3 > -> Sometimes for SMMUv2 > -> No for SMMUv3 (if we go with BIND_PASID_TABLE, which is simpler due to > PASID tables being in GPA space.) > * VFIO_IOMMU_BIND_PASID_TABLE? > -> No for VT-d > -> Sometimes for SMMUv3 > > Any bind support implies VFIO_IOMMU_CACHE_INVALIDATE support. good summary. do you expect to see any > > > >>> + nesting_cap->stage1_formats = formats; > > >> as spotted by Kevin, since a single format is supported, rename > > > > > > ok, I was believing it may be possible on ARM or so. :-) will rename > > > it. > > Yes I don't think an u32 is going to cut it for Arm :( We need to describe all sorts of > capabilities for page and PASID tables (granules, GPA size, ASID/PASID size, HW > access/dirty, etc etc.) Just saying "Arm stage-1 format" wouldn't mean much. I > guess we could have a secondary vendor capability for these? Actually, I'm wondering if we can define some formats to stands for a set of capabilities. e.g. VTD_STAGE1_FORMAT_V1 which may indicates the 1st level page table related caps (aw, a/d, SRE, EA and etc.). And vIOMMU can parse the capabilities. Regards, Yi Liu _______________________________________________ iommu mailing list iommu@lists.linux-foundation.org https://lists.linuxfoundation.org/mailman/listinfo/iommu