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From: Bharat Kumar Gogada <bharatku-gjFFaj9aHVfQT0dZR+AlfA@public.gmane.org>
To: Jean-Philippe Brucker
	<jean-philippe.brucker-5wv7dgnIgG8@public.gmane.org>,
	"linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org"
	<linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org>,
	"linux-pci-u79uwXL29TY76Z2rM5mHXA@public.gmane.org"
	<linux-pci-u79uwXL29TY76Z2rM5mHXA@public.gmane.org>,
	"linux-acpi-u79uwXL29TY76Z2rM5mHXA@public.gmane.org"
	<linux-acpi-u79uwXL29TY76Z2rM5mHXA@public.gmane.org>,
	"devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org"
	<devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org>,
	"iommu-cunTk1MwBs9QetFLy7KEm3xJsTq8ys+cHZ5vskTnxNA@public.gmane.org"
	<iommu-cunTk1MwBs9QetFLy7KEm3xJsTq8ys+cHZ5vskTnxNA@public.gmane.org>,
	"kvm-u79uwXL29TY76Z2rM5mHXA@public.gmane.org"
	<kvm-u79uwXL29TY76Z2rM5mHXA@public.gmane.org>,
	"linux-mm-Bw31MaZKKs3YtjvyW6yDsg@public.gmane.org"
	<linux-mm-Bw31MaZKKs3YtjvyW6yDsg@public.gmane.org>
Cc: "xuzaibo-hv44wF8Li93QT0dZR+AlfA@public.gmane.org"
	<xuzaibo-hv44wF8Li93QT0dZR+AlfA@public.gmane.org>,
	"will.deacon-5wv7dgnIgG8@public.gmane.org"
	<will.deacon-5wv7dgnIgG8@public.gmane.org>,
	"okaya-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org"
	<okaya-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>,
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	<ashok.raj-ral2JQCrhuEAvxtiuMwx3w@public.gmane.org>,
	"rfranz-YGCgFSpz5w/QT0dZR+AlfA@public.gmane.org"
	<rfranz-YGCgFSpz5w/QT0dZR+AlfA@public.gmane.org>,
	Ravikiran Gummaluri
	<rgummal-gjFFaj9aHVfQT0dZR+AlfA@public.gmane.org>,
	"ilias.apalodimas-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org"
	<ilias.apalodimas-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>,
	"dwmw2-wEGCiKHe2LqWVfeAwA7xHQ@public.gmane.org"
	<dwmw2-wEGCiKHe2LqWVfeAwA7xHQ@public.gmane.org>,
	"christian.koenig-5C7GfCeVMHo@public.gmane.org"
	<christian.koenig-5C7GfCeVMHo@public.gmane.org>
Subject: RE: [PATCH v2 21/40] iommu/arm-smmu-v3: Add support for Substream IDs
Date: Thu, 31 May 2018 11:01:22 +0000
Message-ID: <BLUPR0201MB1505AA55707BE2E13392FFAFA5630@BLUPR0201MB1505.namprd02.prod.outlook.com> (raw)
In-Reply-To: <20180511190641.23008-22-jean-philippe.brucker-5wv7dgnIgG8@public.gmane.org>

> 
> At the moment, the SMMUv3 driver offers only one stage-1 or stage-2
> address space to each device. SMMUv3 allows to associate multiple address
> spaces per device. In addition to the Stream ID (SID), that identifies a device,
> we can now have Substream IDs (SSID) identifying an address space.
> In PCIe lingo, SID is called Requester ID (RID) and SSID is called Process
> Address-Space ID (PASID).
> 
> Prepare the driver for SSID support, by adding context descriptor tables in
> STEs (previously a single static context descriptor). A complete
> stage-1 walk is now performed like this by the SMMU:
> 
>       Stream tables          Ctx. tables          Page tables
>         +--------+   ,------->+-------+   ,------->+-------+
>         :        :   |        :       :   |        :       :
>         +--------+   |        +-------+   |        +-------+
>    SID->|  STE   |---'  SSID->|  CD   |---'  IOVA->|  PTE  |--> IPA
>         +--------+            +-------+            +-------+
>         :        :            :       :            :       :
>         +--------+            +-------+            +-------+
> 
> We only implement one level of context descriptor table for now, but as with
> stream and page tables, an SSID can be split to target multiple levels of
> tables.
> 
> In all stream table entries, we set S1DSS=SSID0 mode, making translations
> without an ssid use context descriptor 0.
> 
> Signed-off-by: Jean-Philippe Brucker <jean-philippe.brucker-5wv7dgnIgG8@public.gmane.org>
> 
> ---
> v1->v2: use GENMASK throughout SMMU patches
> ---
>  drivers/iommu/arm-smmu-v3-context.c | 141 +++++++++++++++++++++------
> -
>  drivers/iommu/arm-smmu-v3.c         |  82 +++++++++++++++-
>  drivers/iommu/iommu-pasid-table.h   |   7 ++
>  3 files changed, 190 insertions(+), 40 deletions(-)
> 
> diff --git a/drivers/iommu/arm-smmu-v3-context.c b/drivers/iommu/arm-
> smmu-v3-context.c
> index 15d3d02c59b2..0969a3626110 100644
> --- a/drivers/iommu/arm-smmu-v3-context.c
> +++ b/drivers/iommu/arm-smmu-v3-context.c
> @@ -62,11 +62,14 @@ struct arm_smmu_cd {  #define
> pasid_entry_to_cd(entry) \
>  	container_of((entry), struct arm_smmu_cd, entry)
> 
> +struct arm_smmu_cd_table {
> +	__le64				*ptr;
> +	dma_addr_t			ptr_dma;
> +};
> +
>  struct arm_smmu_cd_tables {
>  	struct iommu_pasid_table	pasid;
> -
> -	void				*ptr;
> -	dma_addr_t			ptr_dma;
> +	struct arm_smmu_cd_table	table;
>  };
> 
>  #define pasid_to_cd_tables(pasid_table) \ @@ -77,6 +80,36 @@ struct
> arm_smmu_cd_tables {
> 
>  static DEFINE_IDA(asid_ida);
> 
> +static int arm_smmu_alloc_cd_leaf_table(struct device *dev,
> +					struct arm_smmu_cd_table *desc,
> +					size_t num_entries)
> +{
> +	size_t size = num_entries * (CTXDESC_CD_DWORDS << 3);
> +
> +	desc->ptr = dmam_alloc_coherent(dev, size, &desc->ptr_dma,
> +					GFP_ATOMIC | __GFP_ZERO);
> +	if (!desc->ptr) {
> +		dev_warn(dev, "failed to allocate context descriptor
> table\n");
> +		return -ENOMEM;
> +	}
> +
> +	return 0;
> +}
> +
> +static void arm_smmu_free_cd_leaf_table(struct device *dev,
> +					struct arm_smmu_cd_table *desc,
> +					size_t num_entries)
> +{
> +	size_t size = num_entries * (CTXDESC_CD_DWORDS << 3);
> +
> +	dmam_free_coherent(dev, size, desc->ptr, desc->ptr_dma); }
> +
> +static __le64 *arm_smmu_get_cd_ptr(struct arm_smmu_cd_tables *tbl,
> u32
> +ssid) {
> +	return tbl->table.ptr + ssid * CTXDESC_CD_DWORDS; }
> +
>  static u64 arm_smmu_cpu_tcr_to_cd(u64 tcr)  {
>  	u64 val = 0;
> @@ -95,34 +128,74 @@ static u64 arm_smmu_cpu_tcr_to_cd(u64 tcr)
>  	return val;
>  }
> 
> -static void arm_smmu_write_ctx_desc(struct arm_smmu_cd_tables *tbl,
> -				    struct arm_smmu_cd *cd)
> +static int arm_smmu_write_ctx_desc(struct arm_smmu_cd_tables *tbl, int
> ssid,
> +				   struct arm_smmu_cd *cd)
>  {
>  	u64 val;
> -	__u64 *cdptr = tbl->ptr;
> +	bool cd_live;
> +	__le64 *cdptr = arm_smmu_get_cd_ptr(tbl, ssid);
>  	struct arm_smmu_context_cfg *cfg = &tbl->pasid.cfg.arm_smmu;
> 
>  	/*
> -	 * We don't need to issue any invalidation here, as we'll invalidate
> -	 * the STE when installing the new entry anyway.
> +	 * This function handles the following cases:
> +	 *
> +	 * (1) Install primary CD, for normal DMA traffic (SSID = 0).
> +	 * (2) Install a secondary CD, for SID+SSID traffic, followed by an
> +	 *     invalidation.
> +	 * (3) Update ASID of primary CD. This is allowed by atomically
> writing
> +	 *     the first 64 bits of the CD, followed by invalidation of the old
> +	 *     entry and mappings.
> +	 * (4) Remove a secondary CD and invalidate it.
>  	 */
> -	val = arm_smmu_cpu_tcr_to_cd(cd->tcr) |
> +
> +	if (!cdptr)
> +		return -ENOMEM;
> +
> +	val = le64_to_cpu(cdptr[0]);
> +	cd_live = !!(val & CTXDESC_CD_0_V);
> +
> +	if (!cd) { /* (4) */
> +		cdptr[0] = 0;
> +	} else if (cd_live) { /* (3) */
> +		val &= ~CTXDESC_CD_0_ASID;
> +		val |= FIELD_PREP(CTXDESC_CD_0_ASID, cd->entry.tag);
> +
> +		cdptr[0] = cpu_to_le64(val);
> +		/*
> +		 * Until CD+TLB invalidation, both ASIDs may be used for
> tagging
> +		 * this substream's traffic
> +		 */
> +	} else { /* (1) and (2) */
> +		cdptr[1] = cpu_to_le64(cd->ttbr &
> CTXDESC_CD_1_TTB0_MASK);
> +		cdptr[2] = 0;
> +		cdptr[3] = cpu_to_le64(cd->mair);
> +
> +		/*
> +		 * STE is live, and the SMMU might fetch this CD at any
> +		 * time. Ensure it observes the rest of the CD before we
> +		 * enable it.
> +		 */
> +		iommu_pasid_flush(&tbl->pasid, ssid, true);
> +
> +
> +		val = arm_smmu_cpu_tcr_to_cd(cd->tcr) |
>  #ifdef __BIG_ENDIAN
> -	      CTXDESC_CD_0_ENDI |
> +		      CTXDESC_CD_0_ENDI |
>  #endif
> -	      CTXDESC_CD_0_R | CTXDESC_CD_0_A | CTXDESC_CD_0_ASET |
> -	      CTXDESC_CD_0_AA64 | FIELD_PREP(CTXDESC_CD_0_ASID, cd-
> >entry.tag) |
> -	      CTXDESC_CD_0_V;
> +		      CTXDESC_CD_0_R | CTXDESC_CD_0_A |
> CTXDESC_CD_0_ASET |
> +		      CTXDESC_CD_0_AA64 |
> +		      FIELD_PREP(CTXDESC_CD_0_ASID, cd->entry.tag) |
> +		      CTXDESC_CD_0_V;
> 
> -	if (cfg->stall)
> -		val |= CTXDESC_CD_0_S;
> +		if (cfg->stall)
> +			val |= CTXDESC_CD_0_S;
> 
> -	cdptr[0] = cpu_to_le64(val);
> +		cdptr[0] = cpu_to_le64(val);
> +	}
> 
> -	val = cd->ttbr & CTXDESC_CD_1_TTB0_MASK;
> -	cdptr[1] = cpu_to_le64(val);
> +	iommu_pasid_flush(&tbl->pasid, ssid, true);
> 
> -	cdptr[3] = cpu_to_le64(cd->mair);
> +	return 0;
>  }
> 
>  static void arm_smmu_free_cd(struct iommu_pasid_entry *entry) @@ -
> 190,8 +263,10 @@ static int arm_smmu_set_cd(struct
> iommu_pasid_table_ops *ops, int pasid,
>  	struct arm_smmu_cd_tables *tbl = pasid_ops_to_tables(ops);
>  	struct arm_smmu_cd *cd = pasid_entry_to_cd(entry);
> 
> -	arm_smmu_write_ctx_desc(tbl, cd);
> -	return 0;
> +	if (WARN_ON(pasid > (1 << tbl->pasid.cfg.order)))
> +		return -EINVAL;
> +
> +	return arm_smmu_write_ctx_desc(tbl, pasid, cd);
>  }
> 
>  static void arm_smmu_clear_cd(struct iommu_pasid_table_ops *ops, int
> pasid, @@ -199,30 +274,26 @@ static void arm_smmu_clear_cd(struct
> iommu_pasid_table_ops *ops, int pasid,  {
>  	struct arm_smmu_cd_tables *tbl = pasid_ops_to_tables(ops);
> 
> -	arm_smmu_write_ctx_desc(tbl, NULL);
> +	if (WARN_ON(pasid > (1 << tbl->pasid.cfg.order)))
> +		return;
> +
> +	arm_smmu_write_ctx_desc(tbl, pasid, NULL);
>  }
> 
>  static struct iommu_pasid_table *
>  arm_smmu_alloc_cd_tables(struct iommu_pasid_table_cfg *cfg, void
> *cookie)  {
> +	int ret;
>  	struct arm_smmu_cd_tables *tbl;
>  	struct device *dev = cfg->iommu_dev;
> 
> -	if (cfg->order) {
> -		/* TODO: support SSID */
> -		return NULL;
> -	}
> -
>  	tbl = devm_kzalloc(dev, sizeof(*tbl), GFP_KERNEL);
>  	if (!tbl)
>  		return NULL;
> 
> -	tbl->ptr = dmam_alloc_coherent(dev, CTXDESC_CD_DWORDS << 3,
> -				       &tbl->ptr_dma, GFP_KERNEL |
> __GFP_ZERO);
> -	if (!tbl->ptr) {
> -		dev_warn(dev, "failed to allocate context descriptor\n");
> +	ret = arm_smmu_alloc_cd_leaf_table(dev, &tbl->table, 1 << cfg-
> >order);
> +	if (ret)
>  		goto err_free_tbl;
> -	}
> 
>  	tbl->pasid.ops = (struct iommu_pasid_table_ops) {
>  		.alloc_priv_entry	= arm_smmu_alloc_priv_cd,
> @@ -230,7 +301,8 @@ arm_smmu_alloc_cd_tables(struct
> iommu_pasid_table_cfg *cfg, void *cookie)
>  		.set_entry		= arm_smmu_set_cd,
>  		.clear_entry		= arm_smmu_clear_cd,
>  	};
> -	cfg->base = tbl->ptr_dma;
> +	cfg->base			= tbl->table.ptr_dma;
> +	cfg->arm_smmu.s1fmt		= ARM_SMMU_S1FMT_LINEAR;
> 
>  	return &tbl->pasid;
> 
> @@ -246,8 +318,7 @@ static void arm_smmu_free_cd_tables(struct
> iommu_pasid_table *pasid_table)
>  	struct device *dev = cfg->iommu_dev;
>  	struct arm_smmu_cd_tables *tbl = pasid_to_cd_tables(pasid_table);
> 
> -	dmam_free_coherent(dev, CTXDESC_CD_DWORDS << 3,
> -			   tbl->ptr, tbl->ptr_dma);
> +	arm_smmu_free_cd_leaf_table(dev, &tbl->table, 1 << cfg->order);
>  	devm_kfree(dev, tbl);
>  }
> 
> diff --git a/drivers/iommu/arm-smmu-v3.c b/drivers/iommu/arm-smmu-v3.c
> index 68764a200e44..16b08f2fb8ac 100644
> --- a/drivers/iommu/arm-smmu-v3.c
> +++ b/drivers/iommu/arm-smmu-v3.c
> @@ -224,10 +224,14 @@
>  #define STRTAB_STE_0_CFG_S2_TRANS	6
> 
>  #define STRTAB_STE_0_S1FMT		GENMASK_ULL(5, 4)
> -#define STRTAB_STE_0_S1FMT_LINEAR	0
>  #define STRTAB_STE_0_S1CTXPTR_MASK	GENMASK_ULL(51, 6)
>  #define STRTAB_STE_0_S1CDMAX		GENMASK_ULL(63, 59)
> 
> +#define STRTAB_STE_1_S1DSS		GENMASK_ULL(1, 0)
> +#define STRTAB_STE_1_S1DSS_TERMINATE	0x0
> +#define STRTAB_STE_1_S1DSS_BYPASS	0x1
> +#define STRTAB_STE_1_S1DSS_SSID0	0x2
> +
>  #define STRTAB_STE_1_S1C_CACHE_NC	0UL
>  #define STRTAB_STE_1_S1C_CACHE_WBRA	1UL
>  #define STRTAB_STE_1_S1C_CACHE_WT	2UL
> @@ -275,6 +279,7 @@
>  #define CMDQ_PREFETCH_1_SIZE		GENMASK_ULL(4, 0)
>  #define CMDQ_PREFETCH_1_ADDR_MASK	GENMASK_ULL(63, 12)
> 
> +#define CMDQ_CFGI_0_SSID		GENMASK_ULL(31, 12)
>  #define CMDQ_CFGI_0_SID			GENMASK_ULL(63, 32)
>  #define CMDQ_CFGI_1_LEAF		(1UL << 0)
>  #define CMDQ_CFGI_1_RANGE		GENMASK_ULL(4, 0)
> @@ -381,8 +386,11 @@ struct arm_smmu_cmdq_ent {
> 
>  		#define CMDQ_OP_CFGI_STE	0x3
>  		#define CMDQ_OP_CFGI_ALL	0x4
> +		#define CMDQ_OP_CFGI_CD		0x5
> +		#define CMDQ_OP_CFGI_CD_ALL	0x6
>  		struct {
>  			u32			sid;
> +			u32			ssid;
>  			union {
>  				bool		leaf;
>  				u8		span;
> @@ -555,6 +563,7 @@ struct arm_smmu_master_data {
>  	struct list_head		list; /* domain->devices */
> 
>  	struct device			*dev;
> +	size_t				ssid_bits;
>  };
> 
>  /* SMMU private data for an IOMMU domain */ @@ -753,10 +762,16 @@
> static int arm_smmu_cmdq_build_cmd(u64 *cmd, struct
> arm_smmu_cmdq_ent *ent)
>  		cmd[1] |= FIELD_PREP(CMDQ_PREFETCH_1_SIZE, ent-
> >prefetch.size);
>  		cmd[1] |= ent->prefetch.addr &
> CMDQ_PREFETCH_1_ADDR_MASK;
>  		break;
> +	case CMDQ_OP_CFGI_CD:
> +		cmd[0] |= FIELD_PREP(CMDQ_CFGI_0_SSID, ent->cfgi.ssid);
> +		/* Fallthrough */
>  	case CMDQ_OP_CFGI_STE:
>  		cmd[0] |= FIELD_PREP(CMDQ_CFGI_0_SID, ent->cfgi.sid);
>  		cmd[1] |= FIELD_PREP(CMDQ_CFGI_1_LEAF, ent->cfgi.leaf);
>  		break;
> +	case CMDQ_OP_CFGI_CD_ALL:
> +		cmd[0] |= FIELD_PREP(CMDQ_CFGI_0_SID, ent->cfgi.sid);
> +		break;
>  	case CMDQ_OP_CFGI_ALL:
>  		/* Cover the entire SID range */
>  		cmd[1] |= FIELD_PREP(CMDQ_CFGI_1_RANGE, 31); @@ -
> 1048,8 +1063,11 @@ static void arm_smmu_write_strtab_ent(struct
> arm_smmu_device *smmu, u32 sid,
>  	}
> 
>  	if (ste->s1_cfg) {
> +		struct iommu_pasid_table_cfg *cfg = &ste->s1_cfg->tables;
> +
>  		BUG_ON(ste_live);
>  		dst[1] = cpu_to_le64(
> +			 FIELD_PREP(STRTAB_STE_1_S1DSS,
> STRTAB_STE_1_S1DSS_SSID0) |
>  			 FIELD_PREP(STRTAB_STE_1_S1CIR,
> STRTAB_STE_1_S1C_CACHE_WBRA) |
>  			 FIELD_PREP(STRTAB_STE_1_S1COR,
> STRTAB_STE_1_S1C_CACHE_WBRA) |
>  			 FIELD_PREP(STRTAB_STE_1_S1CSH,
> ARM_SMMU_SH_ISH) | @@ -1063,7 +1081,9 @@ static void
> arm_smmu_write_strtab_ent(struct arm_smmu_device *smmu, u32 sid,
>  			dst[1] |= cpu_to_le64(STRTAB_STE_1_S1STALLD);
> 
>  		val |= (ste->s1_cfg->tables.base &
> STRTAB_STE_0_S1CTXPTR_MASK) |
> -			FIELD_PREP(STRTAB_STE_0_CFG,
> STRTAB_STE_0_CFG_S1_TRANS);
> +			FIELD_PREP(STRTAB_STE_0_CFG,
> STRTAB_STE_0_CFG_S1_TRANS) |
> +			FIELD_PREP(STRTAB_STE_0_S1CDMAX, cfg->order) |
> +			FIELD_PREP(STRTAB_STE_0_S1FMT, cfg-
> >arm_smmu.s1fmt);
>  	}
> 
>  	if (ste->s2_cfg) {
> @@ -1352,17 +1372,62 @@ static const struct iommu_gather_ops
> arm_smmu_gather_ops = {  };
> 
>  /* PASID TABLE API */
> +static void __arm_smmu_sync_cd(struct arm_smmu_domain
> *smmu_domain,
> +			       struct arm_smmu_cmdq_ent *cmd) {
> +	size_t i;
> +	unsigned long flags;
> +	struct arm_smmu_master_data *master;
> +	struct arm_smmu_device *smmu = smmu_domain->smmu;
> +
> +	spin_lock_irqsave(&smmu_domain->devices_lock, flags);
> +	list_for_each_entry(master, &smmu_domain->devices, list) {
> +		struct iommu_fwspec *fwspec = master->dev-
> >iommu_fwspec;
> +
> +		for (i = 0; i < fwspec->num_ids; i++) {
> +			cmd->cfgi.sid = fwspec->ids[i];
> +			arm_smmu_cmdq_issue_cmd(smmu, cmd);
> +		}
> +	}
> +	spin_unlock_irqrestore(&smmu_domain->devices_lock, flags);
> +
> +	__arm_smmu_tlb_sync(smmu);
> +}
> +
>  static void arm_smmu_sync_cd(void *cookie, int ssid, bool leaf)  {
> +	struct arm_smmu_cmdq_ent cmd = {
> +		.opcode	= CMDQ_OP_CFGI_CD_ALL,

Hi Jean, here CMDQ_OP_CFGI_CD opcode 0x5. 

> +		.cfgi	= {
> +			.ssid	= ssid,
> +			.leaf	= leaf,
> +		},
> +	};
> +
> +	__arm_smmu_sync_cd(cookie, &cmd);
>  }
> 

Regards,
Bharat

  parent reply index

Thread overview: 123+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-05-11 19:06 [PATCH v2 00/40] Shared Virtual Addressing for the IOMMU Jean-Philippe Brucker
     [not found] ` <20180511190641.23008-1-jean-philippe.brucker-5wv7dgnIgG8@public.gmane.org>
2018-05-11 19:06   ` [PATCH v2 01/40] iommu: Introduce Shared Virtual Addressing API Jean-Philippe Brucker
     [not found]     ` <20180511190641.23008-2-jean-philippe.brucker-5wv7dgnIgG8@public.gmane.org>
2018-05-16 20:41       ` Jacob Pan
2018-05-17 10:02         ` Jean-Philippe Brucker
2018-05-17 17:00           ` Jacob Pan
2018-09-05 11:29       ` Auger Eric
     [not found]         ` <bf42affd-e9d0-e4fc-6d28-f3c3f7795348-H+wXaHxf7aLQT0dZR+AlfA@public.gmane.org>
2018-09-06 11:09           ` Jean-Philippe Brucker
     [not found]             ` <03d31ba5-1eda-ea86-8c0c-91d14c86fe83-5wv7dgnIgG8@public.gmane.org>
2018-09-06 11:12               ` Christian König
     [not found]                 ` <ed39159c-087e-7e56-7d29-d1de9fa1677f-5C7GfCeVMHo@public.gmane.org>
2018-09-06 12:45                   ` Jean-Philippe Brucker
     [not found]                     ` <f0b317d5-e2e9-5478-952c-05e8b97bd68b-5wv7dgnIgG8@public.gmane.org>
2018-09-07  8:55                       ` Christian König
     [not found]                         ` <2fd4a0a1-1a35-bf82-df84-b995cce011d9-5C7GfCeVMHo@public.gmane.org>
2018-09-07 15:45                           ` Jean-Philippe Brucker
     [not found]                             ` <65e7accd-4446-19f5-c667-c6407e89cfa6-5wv7dgnIgG8@public.gmane.org>
2018-09-07 18:02                               ` Christian König
     [not found]                                 ` <5bbc0332-b94b-75cc-ca42-a9b196811daf-5C7GfCeVMHo@public.gmane.org>
2018-09-07 21:25                                   ` Jacob Pan
2018-09-08  7:29                                     ` Christian König
     [not found]                                       ` <3e3a6797-a233-911b-3a7d-d9b549160960-5C7GfCeVMHo@public.gmane.org>
2018-09-12 12:40                                         ` Jean-Philippe Brucker
     [not found]                                           ` <9445a0be-fb5b-d195-4fdf-7ad6cb36ef4f-5wv7dgnIgG8@public.gmane.org>
2018-09-12 12:56                                             ` Christian König
2018-09-13  7:15                                     ` Tian, Kevin
2018-09-13  7:26                           ` Tian, Kevin
2018-05-11 19:06   ` [PATCH v2 02/40] iommu/sva: Bind process address spaces to devices Jean-Philippe Brucker
     [not found]     ` <20180511190641.23008-3-jean-philippe.brucker-5wv7dgnIgG8@public.gmane.org>
2018-05-17 13:10       ` Jonathan Cameron
     [not found]         ` <20180517141058.00001c76-hv44wF8Li93QT0dZR+AlfA@public.gmane.org>
2018-05-21 14:43           ` Jean-Philippe Brucker
2018-09-05 11:29       ` Auger Eric
     [not found]         ` <471873d4-a1a6-1a3a-cf17-1e686b4ade96-H+wXaHxf7aLQT0dZR+AlfA@public.gmane.org>
2018-09-06 11:09           ` Jean-Philippe Brucker
2018-05-11 19:06   ` [PATCH v2 03/40] iommu/sva: Manage process address spaces Jean-Philippe Brucker
     [not found]     ` <20180511190641.23008-4-jean-philippe.brucker-5wv7dgnIgG8@public.gmane.org>
2018-05-16 23:31       ` Jacob Pan
2018-05-17 10:02         ` Jean-Philippe Brucker
     [not found]           ` <de478769-9f7a-d40b-a55e-e2c63ad883e8-5wv7dgnIgG8@public.gmane.org>
2018-05-22 16:43             ` Jacob Pan
2018-05-24 11:44               ` Jean-Philippe Brucker
2018-05-24 11:50                 ` Ilias Apalodimas
2018-05-24 15:04                   ` Jean-Philippe Brucker
     [not found]                     ` <19e82a74-429a-3f86-119e-32b12082d0ff-5wv7dgnIgG8@public.gmane.org>
2018-05-25  6:33                       ` Ilias Apalodimas
2018-05-25  8:39                         ` Jonathan Cameron
     [not found]                           ` <20180525093959.000040a7-hv44wF8Li93QT0dZR+AlfA@public.gmane.org>
2018-05-26  2:24                             ` Kenneth Lee
2018-05-26  2:24                           ` Kenneth Lee
     [not found]                           ` <20180526022445.GA6069@kllp05>
2018-06-11 16:10                             ` Kenneth Lee
2018-06-11 16:10                             ` Kenneth Lee
2018-06-11 16:32                           ` Kenneth Lee
2018-05-17 14:25       ` Jonathan Cameron
     [not found]         ` <20180517150516.000067ca-hv44wF8Li93QT0dZR+AlfA@public.gmane.org>
2018-05-21 14:44           ` Jean-Philippe Brucker
2018-09-05 12:14       ` Auger Eric
     [not found]         ` <d785ec89-6743-d0f1-1a7f-85599a033e5b-H+wXaHxf7aLQT0dZR+AlfA@public.gmane.org>
2018-09-05 18:18           ` Jacob Pan
2018-09-06 17:40             ` Jean-Philippe Brucker
2018-09-06 11:10           ` Jean-Philippe Brucker
2018-05-11 19:06   ` [PATCH v2 04/40] iommu/sva: Add a mm_exit callback for device drivers Jean-Philippe Brucker
     [not found]     ` <20180511190641.23008-5-jean-philippe.brucker-5wv7dgnIgG8@public.gmane.org>
2018-09-05 13:23       ` Auger Eric
     [not found]         ` <d1dc28c4-7742-9c41-3f91-3fbcb8b13c1c-H+wXaHxf7aLQT0dZR+AlfA@public.gmane.org>
2018-09-06 11:10           ` Jean-Philippe Brucker
2018-05-11 19:06   ` [PATCH v2 05/40] iommu/sva: Track mm changes with an MMU notifier Jean-Philippe Brucker
     [not found]     ` <20180511190641.23008-6-jean-philippe.brucker-5wv7dgnIgG8@public.gmane.org>
2018-05-17 14:25       ` Jonathan Cameron
     [not found]         ` <20180517152514.00004247-hv44wF8Li93QT0dZR+AlfA@public.gmane.org>
2018-05-21 14:44           ` Jean-Philippe Brucker
2018-05-11 19:06   ` [PATCH v2 06/40] iommu/sva: Search mm by PASID Jean-Philippe Brucker
2018-05-11 19:06   ` [PATCH v2 07/40] iommu: Add a page fault handler Jean-Philippe Brucker
     [not found]     ` <20180511190641.23008-8-jean-philippe.brucker-5wv7dgnIgG8@public.gmane.org>
2018-05-17 15:25       ` Jonathan Cameron
     [not found]         ` <20180517162555.00002bd3-hv44wF8Li93QT0dZR+AlfA@public.gmane.org>
2018-05-21 14:48           ` Jean-Philippe Brucker
2018-05-18 18:04       ` Jacob Pan
2018-05-21 14:49         ` Jean-Philippe Brucker
     [not found]           ` <8a640794-a6f3-fa01-82a9-06479a6f779a-5wv7dgnIgG8@public.gmane.org>
2018-05-22 23:35             ` Jacob Pan
2018-05-24 11:44               ` Jean-Philippe Brucker
     [not found]                 ` <bdf9f221-ab97-2168-d072-b7f6a0dba840-5wv7dgnIgG8@public.gmane.org>
2018-05-26  0:35                   ` Jacob Pan
2018-05-29 10:00                     ` Jean-Philippe Brucker
2018-05-11 19:06   ` [PATCH v2 08/40] iommu/iopf: Handle mm faults Jean-Philippe Brucker
2018-05-11 19:06   ` [PATCH v2 09/40] iommu/sva: Register page fault handler Jean-Philippe Brucker
2018-05-11 19:06   ` [PATCH v2 10/40] mm: export symbol mm_access Jean-Philippe Brucker
2018-05-11 19:06   ` [PATCH v2 11/40] mm: export symbol find_get_task_by_vpid Jean-Philippe Brucker
2018-05-11 19:06   ` [PATCH v2 12/40] mm: export symbol mmput_async Jean-Philippe Brucker
2018-05-11 19:06   ` [PATCH v2 13/40] vfio: Add support for Shared Virtual Addressing Jean-Philippe Brucker
     [not found]     ` <20180511190641.23008-14-jean-philippe.brucker-5wv7dgnIgG8@public.gmane.org>
2018-05-17 15:58       ` Jonathan Cameron
     [not found]         ` <20180517165845.00000cc9-hv44wF8Li93QT0dZR+AlfA@public.gmane.org>
2018-05-21 14:51           ` Jean-Philippe Brucker
2018-05-23  9:38       ` Xu Zaibo
     [not found]         ` <5B0536A3.1000304-hv44wF8Li93QT0dZR+AlfA@public.gmane.org>
2018-05-24 11:44           ` Jean-Philippe Brucker
     [not found]             ` <cd13f60d-b282-3804-4ca7-2d34476c597f-5wv7dgnIgG8@public.gmane.org>
2018-05-24 12:35               ` Xu Zaibo
     [not found]                 ` <5B06B17C.1090809-hv44wF8Li93QT0dZR+AlfA@public.gmane.org>
2018-05-24 15:04                   ` Jean-Philippe Brucker
     [not found]                     ` <205c1729-8026-3efe-c363-d37d7150d622-5wv7dgnIgG8@public.gmane.org>
2018-05-25  2:39                       ` Xu Zaibo
2018-05-25  9:47                         ` Jean-Philippe Brucker
     [not found]                           ` <fea420ff-e738-e2ed-ab1e-a3f4dde4b6ef-5wv7dgnIgG8@public.gmane.org>
2018-05-26  3:53                             ` Xu Zaibo
     [not found]                               ` <5B08DA21.3070507-hv44wF8Li93QT0dZR+AlfA@public.gmane.org>
2018-05-29 11:55                                 ` Jean-Philippe Brucker
     [not found]                                   ` <99ff4f89-86ef-a251-894c-8aa8a47d2a69-5wv7dgnIgG8@public.gmane.org>
2018-05-29 12:24                                     ` Xu Zaibo
2018-08-27  8:06       ` Xu Zaibo
     [not found]         ` <5B83B11E.7010807-hv44wF8Li93QT0dZR+AlfA@public.gmane.org>
2018-08-31 13:34           ` Jean-Philippe Brucker
     [not found]             ` <1d5b6529-4e5a-723c-3f1b-dd5a9adb490c-5wv7dgnIgG8@public.gmane.org>
2018-09-01  2:23               ` Xu Zaibo
     [not found]                 ` <5B89F818.7060300-hv44wF8Li93QT0dZR+AlfA@public.gmane.org>
2018-09-03 10:34                   ` Jean-Philippe Brucker
     [not found]                     ` <3a961aff-e830-64bb-b6a9-14e08de1abf5-5wv7dgnIgG8@public.gmane.org>
2018-09-04  2:12                       ` Xu Zaibo
     [not found]                         ` <5B8DEA15.7020404-hv44wF8Li93QT0dZR+AlfA@public.gmane.org>
2018-09-04 10:57                           ` Jean-Philippe Brucker
     [not found]                             ` <bc27f902-4d12-21b7-b9e9-18bcae170503-5wv7dgnIgG8@public.gmane.org>
2018-09-05  3:15                               ` Xu Zaibo
     [not found]                                 ` <5B8F4A59.20004-hv44wF8Li93QT0dZR+AlfA@public.gmane.org>
2018-09-05 11:02                                   ` Jean-Philippe Brucker
     [not found]                                     ` <b51107b8-a525-13ce-f4c3-d423b8502c27-5wv7dgnIgG8@public.gmane.org>
2018-09-06  7:26                                       ` Xu Zaibo
2018-05-11 19:06   ` [PATCH v2 14/40] dt-bindings: document stall and PASID properties for IOMMU masters Jean-Philippe Brucker
2018-05-11 19:06   ` [PATCH v2 15/40] iommu/of: Add stall and pasid properties to iommu_fwspec Jean-Philippe Brucker
2018-05-11 19:06   ` [PATCH v2 16/40] arm64: mm: Pin down ASIDs for sharing mm with devices Jean-Philippe Brucker
     [not found]     ` <20180511190641.23008-17-jean-philippe.brucker-5wv7dgnIgG8@public.gmane.org>
2018-05-15 14:16       ` Catalin Marinas
     [not found]         ` <20180515141658.vivrgcyww2pxumye-+1aNUgJU5qkijLcmloz0ER/iLCjYCKR+VpNB7YpNyf8@public.gmane.org>
2018-05-17 10:01           ` Jean-Philippe Brucker
2018-05-11 19:06   ` [PATCH v2 17/40] iommu/arm-smmu-v3: Link domains and devices Jean-Philippe Brucker
     [not found]     ` <20180511190641.23008-18-jean-philippe.brucker-5wv7dgnIgG8@public.gmane.org>
2018-05-17 16:07       ` Jonathan Cameron
     [not found]         ` <20180517170748.00004927-hv44wF8Li93QT0dZR+AlfA@public.gmane.org>
2018-05-21 14:49           ` Jean-Philippe Brucker
2018-09-10 15:16       ` Auger Eric
2018-05-11 19:06   ` [PATCH v2 18/40] iommu/io-pgtable-arm: Factor out ARM LPAE register defines Jean-Philippe Brucker
2018-05-11 19:06   ` [PATCH v2 19/40] iommu: Add generic PASID table library Jean-Philippe Brucker
2018-05-11 19:06   ` [PATCH v2 20/40] iommu/arm-smmu-v3: Move context descriptor code Jean-Philippe Brucker
2018-05-11 19:06   ` [PATCH v2 21/40] iommu/arm-smmu-v3: Add support for Substream IDs Jean-Philippe Brucker
     [not found]     ` <20180511190641.23008-22-jean-philippe.brucker-5wv7dgnIgG8@public.gmane.org>
2018-05-31 11:01       ` Bharat Kumar Gogada [this message]
     [not found]         ` <BLUPR0201MB1505AA55707BE2E13392FFAFA5630-hRBPhS1iNj/g9tdZWAsUFxrHTHEw16jenBOFsp37pqbUKgpGm//BTAC/G2K4zDHf@public.gmane.org>
2018-06-01 10:46           ` Jean-Philippe Brucker
2018-05-11 19:06   ` [PATCH v2 22/40] iommu/arm-smmu-v3: Add second level of context descriptor table Jean-Philippe Brucker
2018-05-11 19:06   ` [PATCH v2 23/40] iommu/arm-smmu-v3: Share process page tables Jean-Philippe Brucker
2018-05-11 19:06   ` [PATCH v2 24/40] iommu/arm-smmu-v3: Seize private ASID Jean-Philippe Brucker
2018-05-11 19:06   ` [PATCH v2 25/40] iommu/arm-smmu-v3: Add support for VHE Jean-Philippe Brucker
2018-05-11 19:06   ` [PATCH v2 26/40] iommu/arm-smmu-v3: Enable broadcast TLB maintenance Jean-Philippe Brucker
2018-05-11 19:06   ` [PATCH v2 27/40] iommu/arm-smmu-v3: Add SVA feature checking Jean-Philippe Brucker
2018-05-11 19:06   ` [PATCH v2 28/40] iommu/arm-smmu-v3: Implement mm operations Jean-Philippe Brucker
2018-05-11 19:06   ` [PATCH v2 29/40] iommu/arm-smmu-v3: Add support for Hardware Translation Table Update Jean-Philippe Brucker
2018-05-11 19:06   ` [PATCH v2 30/40] iommu/arm-smmu-v3: Register I/O Page Fault queue Jean-Philippe Brucker
2018-05-11 19:06   ` [PATCH v2 31/40] iommu/arm-smmu-v3: Improve add_device error handling Jean-Philippe Brucker
2018-05-11 19:06   ` [PATCH v2 32/40] iommu/arm-smmu-v3: Maintain a SID->device structure Jean-Philippe Brucker
2018-05-11 19:06   ` [PATCH v2 33/40] iommu/arm-smmu-v3: Add stall support for platform devices Jean-Philippe Brucker
2018-05-11 19:06   ` [PATCH v2 34/40] ACPI/IORT: Check ATS capability in root complex nodes Jean-Philippe Brucker
2018-05-11 19:06   ` [PATCH v2 35/40] iommu/arm-smmu-v3: Add support for PCI ATS Jean-Philippe Brucker
     [not found]     ` <20180511190641.23008-36-jean-philippe.brucker-5wv7dgnIgG8@public.gmane.org>
2018-05-19 17:25       ` Sinan Kaya
     [not found]         ` <922474e8-0aa5-e022-0502-f1e51b0d4859-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>
2018-05-21 14:52           ` Jean-Philippe Brucker
2018-05-11 19:06   ` [PATCH v2 36/40] iommu/arm-smmu-v3: Hook up ATC invalidation to mm ops Jean-Philippe Brucker
2018-05-11 19:06   ` [PATCH v2 37/40] iommu/arm-smmu-v3: Disable tagged pointers Jean-Philippe Brucker
2018-05-11 19:06   ` [PATCH v2 38/40] PCI: Make "PRG Response PASID Required" handling common Jean-Philippe Brucker
2018-05-11 19:06   ` [PATCH v2 39/40] iommu/arm-smmu-v3: Add support for PRI Jean-Philippe Brucker
     [not found]     ` <20180511190641.23008-40-jean-philippe.brucker-5wv7dgnIgG8@public.gmane.org>
2018-05-25 14:08       ` Bharat Kumar Gogada
     [not found]         ` <BLUPR0201MB150513BBAA161355DE9B3A48A5690-hRBPhS1iNj/g9tdZWAsUFxrHTHEw16jenBOFsp37pqbUKgpGm//BTAC/G2K4zDHf@public.gmane.org>
2018-05-29 10:27           ` Jean-Philippe Brucker
2018-05-11 19:06   ` [PATCH v2 40/40] iommu/arm-smmu-v3: Add support for PCI PASID Jean-Philippe Brucker

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