From: "Tian, Kevin" <kevin.tian@intel.com>
To: Lu Baolu <baolu.lu@linux.intel.com>,
"iommu@lists.linux.dev" <iommu@lists.linux.dev>
Cc: Joerg Roedel <joro@8bytes.org>, Will Deacon <will@kernel.org>,
"Robin Murphy" <robin.murphy@arm.com>,
Jacob Pan <jacob.jun.pan@linux.intel.com>,
"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
"Jerry Snitselaar" <jsnitsel@redhat.com>
Subject: RE: [PATCH v2 1/1] iommu/vt-d: Avoid unnecessary global IRTE cache invalidation
Date: Wed, 21 Sep 2022 07:59:04 +0000 [thread overview]
Message-ID: <BN9PR11MB5276117899AB724A2F034ACE8C4F9@BN9PR11MB5276.namprd11.prod.outlook.com> (raw)
In-Reply-To: <20220921065741.3572495-1-baolu.lu@linux.intel.com>
> From: Lu Baolu <baolu.lu@linux.intel.com>
> Sent: Wednesday, September 21, 2022 2:58 PM
>
> Some VT-d hardware implementations invalidate all interrupt remapping
> hardware translation caches as part of SIRTP flow. The VT-d spec adds
> a ESIRTPS (Enhanced Set Interrupt Remap Table Pointer Support, section
> 11.4.2 in VT-d spec) capability bit to indicate this.
>
> The spec also states in 11.4.4 that hardware also performs global
> invalidation on all interrupt remapping caches as part of Interrupt
> Remapping Disable operation if ESIRTPS capability bit is set.
>
> This checks the ESIRTPS capability bit and skip software global cache
> invalidation if it's set.
>
> Signed-off-by: Jacob Pan <jacob.jun.pan@linux.intel.com>
> Signed-off-by: Lu Baolu <baolu.lu@linux.intel.com>
> Reviewed-by: Jerry Snitselaar <jsnitsel@redhat.com>
Reviewed-by: Kevin Tian <kevin.tian@intel.com>
prev parent reply other threads:[~2022-09-21 7:59 UTC|newest]
Thread overview: 2+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-09-21 6:57 [PATCH v2 1/1] iommu/vt-d: Avoid unnecessary global IRTE cache invalidation Lu Baolu
2022-09-21 7:59 ` Tian, Kevin [this message]
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