From: "Tian, Kevin" <kevin.tian@intel.com>
To: Nicolin Chen <nicolinc@nvidia.com>,
"agross@kernel.org" <agross@kernel.org>,
"bjorn.andersson@linaro.org" <bjorn.andersson@linaro.org>,
"konrad.dybcio@somainline.org" <konrad.dybcio@somainline.org>,
"joro@8bytes.org" <joro@8bytes.org>,
"will@kernel.org" <will@kernel.org>,
"robin.murphy@arm.com" <robin.murphy@arm.com>,
"sricharan@codeaurora.org" <sricharan@codeaurora.org>
Cc: "jgg@nvidia.com" <jgg@nvidia.com>,
"linux-arm-msm@vger.kernel.org" <linux-arm-msm@vger.kernel.org>,
"iommu@lists.linux.dev" <iommu@lists.linux.dev>,
"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>
Subject: RE: [PATCH v3 1/6] iommu/msm: Add missing __disable_clocks calls
Date: Tue, 20 Sep 2022 06:15:21 +0000 [thread overview]
Message-ID: <BN9PR11MB52769AEAFD33D2501B6571538C4C9@BN9PR11MB5276.namprd11.prod.outlook.com> (raw)
In-Reply-To: <031c4ec032025a299d72665118d58dd48aa936ac.1663227492.git.nicolinc@nvidia.com>
> From: Nicolin Chen <nicolinc@nvidia.com>
> Sent: Thursday, September 15, 2022 3:56 PM
>
> The clock is not symmetrically disabled in the error-out routines.
>
> Fixes: 109bd48ea2e1 ("iommu/msm: Add DT adaptation")
> Cc: stable@vger.kernel.org
> Cc: Sricharan R <sricharan@codeaurora.org>
> Cc: Andy Gross <agross@kernel.org>
> Cc: Bjorn Andersson <bjorn.andersson@linaro.org>
> Cc: Konrad Dybcio <konrad.dybcio@somainline.org>
> Signed-off-by: Nicolin Chen <nicolinc@nvidia.com>
> ---
> drivers/iommu/msm_iommu.c | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/drivers/iommu/msm_iommu.c b/drivers/iommu/msm_iommu.c
> index 6a24aa804ea3..a7d41ba4a47b 100644
> --- a/drivers/iommu/msm_iommu.c
> +++ b/drivers/iommu/msm_iommu.c
> @@ -418,6 +418,7 @@ static int msm_iommu_attach_dev(struct
> iommu_domain *domain, struct device *dev)
> list_for_each_entry(master, &iommu->ctx_list, list) {
> if (master->num) {
> dev_err(dev, "domain already
> attached");
> + __disable_clocks(iommu);
> ret = -EEXIST;
> goto fail;
> }
> @@ -425,6 +426,7 @@ static int msm_iommu_attach_dev(struct
> iommu_domain *domain, struct device *dev)
> msm_iommu_alloc_ctx(iommu-
> >context_map,
> 0, iommu->ncb);
> if (IS_ERR_VALUE(master->num)) {
> + __disable_clocks(iommu);
also need to free_ctx() for already walked nodes.
btw it's a bit weird that although here is coded based on a list
in reality there is at most one node per list. According to
insert_iommu_master() a master object is allocated and inserted
to the ctx_list only if the ctx_list is currently empty...
> ret = -ENODEV;
> goto fail;
> }
> --
> 2.17.1
next prev parent reply other threads:[~2022-09-20 6:15 UTC|newest]
Thread overview: 19+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-09-15 7:53 [PATCH v3 0/6] Define EINVAL as device/domain incompatibility Nicolin Chen
2022-09-15 7:53 ` [PATCH v3 3/6] iommu: Add return value rules to attach_dev op and APIs Nicolin Chen
2022-09-20 6:24 ` Tian, Kevin
2022-09-20 19:26 ` Nicolin Chen
2022-09-15 7:53 ` [PATCH v3 5/6] iommu: Use EINVAL for incompatible device/domain in ->attach_dev Nicolin Chen
2022-09-20 6:38 ` Tian, Kevin
2022-09-20 18:06 ` Jason Gunthorpe
2022-09-21 8:14 ` Tian, Kevin
2022-09-15 7:56 ` [PATCH v3 1/6] iommu/msm: Add missing __disable_clocks calls Nicolin Chen
2022-09-20 6:15 ` Tian, Kevin [this message]
2022-09-20 18:46 ` Nicolin Chen
2022-09-21 7:27 ` Tian, Kevin
2022-09-15 7:58 ` [PATCH v3 2/6] iommu/amd: Drop unnecessary checks in amd_iommu_attach_device() Nicolin Chen
2022-09-15 7:58 ` [PATCH v3 4/6] iommu: Regulate EINVAL in ->attach_dev callback functions Nicolin Chen
2022-09-20 6:29 ` Tian, Kevin
2022-09-20 16:08 ` Nicolin Chen
2022-09-15 7:58 ` [PATCH v3 6/6] iommu: Propagate ret for a potential soft failure EINVAL Nicolin Chen
2022-09-20 6:50 ` Tian, Kevin
2022-09-20 20:39 ` Nicolin Chen
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