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a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=Mam0jmHC79p3v1pPEObliIl7gHrMe1XbetijSP5zncI=; b=rwTKvCkteuoLsJIdKSpggyr3pJ9UTcD/H4gu0NKzvG7EbafzLt41WU/CEYE8FbXNJ/ HRfTvTSqA0/6QqRxxbjLKisRuRpLOz20x8F7PaU62KKbmT3+PaIP/TfoCjappKG9QMx/ Sd26ATwwjFoDgHPbDVnluIropLg81aPqpef+ckH9Pk6+PPQvSimFyjbP+D3KTK/Z4Mg1 H0KVek3kcXv3ZGBtpbCCZf1oSuEA/U9tcTIBtHibmPeOa4gGGEq72SW9nAK4I/w+D1hr wWLb2x20fmrEMjEzSNR66wYGyHPn3mJv5oAou/ZyhhYkDJVu9QQbA5W1+HxXt0VoIQFC ZYfg== X-Gm-Message-State: AOAM5302dMiM7ukfjKlcn4xpINiXgC3Ko2nCo3tiVv9IXsQYrhP/L0+g dG8/9o2yxuKoYtGiY1zM52vzuJpCggMhIdjsZgM= X-Google-Smtp-Source: ABdhPJwAak2gmrJ75fYqfKG002IIAJ3g+T9yn75xNxFIQ0i05jgSdssvyWPSh4oXD0jc4sg7my3h0ep4LvxCtfrPbVs= X-Received: by 2002:aa7:c38f:: with SMTP id k15mr482553edq.7.1589817009296; Mon, 18 May 2020 08:50:09 -0700 (PDT) MIME-Version: 1.0 References: <1580249770-1088-1-git-send-email-jcrouse@codeaurora.org> <1580249770-1088-3-git-send-email-jcrouse@codeaurora.org> <20200318224840.GA10796@willie-the-truck> <20200518151838.GL32394@willie-the-truck> In-Reply-To: <20200518151838.GL32394@willie-the-truck> From: Rob Clark Date: Mon, 18 May 2020 08:50:27 -0700 Message-ID: Subject: Re: [PATCH v1 2/6] arm/smmu: Add auxiliary domain support for arm-smmuv2 To: Will Deacon Cc: linux-arm-msm , Linux Kernel Mailing List , "list@263.net:IOMMU DRIVERS , Joerg Roedel , " , Robin Murphy , "moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE" X-BeenThere: iommu@lists.linux-foundation.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: Development issues for Linux IOMMU support List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Errors-To: iommu-bounces@lists.linux-foundation.org Sender: "iommu" On Mon, May 18, 2020 at 8:18 AM Will Deacon wrote: > > On Wed, Mar 18, 2020 at 04:43:07PM -0700, Rob Clark wrote: > > On Wed, Mar 18, 2020 at 3:48 PM Will Deacon wrote: > > > On Tue, Jan 28, 2020 at 03:16:06PM -0700, Jordan Crouse wrote: > > > > Support auxiliary domains for arm-smmu-v2 to initialize and support > > > > multiple pagetables for a single SMMU context bank. Since the smmu-v2 > > > > hardware doesn't have any built in support for switching the pagetable > > > > base it is left as an exercise to the caller to actually use the pagetable. > > > > > > > > Aux domains are supported if split pagetable (TTBR1) support has been > > > > enabled on the master domain. Each auxiliary domain will reuse the > > > > configuration of the master domain. By default the a domain with TTBR1 > > > > support will have the TTBR0 region disabled so the first attached aux > > > > domain will enable the TTBR0 region in the hardware and conversely the > > > > last domain to be detached will disable TTBR0 translations. All subsequent > > > > auxiliary domains create a pagetable but not touch the hardware. > > > > > > > > The leaf driver will be able to query the physical address of the > > > > pagetable with the DOMAIN_ATTR_PTBASE attribute so that it can use the > > > > address with whatever means it has to switch the pagetable base. > > > > > > > > Following is a pseudo code example of how a domain can be created > > > > > > > > /* Check to see if aux domains are supported */ > > > > if (iommu_dev_has_feature(dev, IOMMU_DEV_FEAT_AUX)) { > > > > iommu = iommu_domain_alloc(...); > > > > > > > > if (iommu_aux_attach_device(domain, dev)) > > > > return FAIL; > > > > > > > > /* Save the base address of the pagetable for use by the driver > > > > iommu_domain_get_attr(domain, DOMAIN_ATTR_PTBASE, &ptbase); > > > > } > > > > > > I'm not really understanding what the pagetable base gets used for here and, > > > to be honest with you, the whole thing feels like a huge layering violation > > > with the way things are structured today. Why doesn't the caller just > > > interface with io-pgtable directly? > > > > > > Finally, if we need to support context-switching TTBR0 for a live domain > > > then that code really needs to live inside the SMMU driver because the > > > ASID and TLB management necessary to do that safely doesn't belong anywhere > > > else. > > > > We do in fact need live domain switching, that is really the whole > > point. The GPU CP (command processor/parser) is directly updating > > TTBR0 and triggering TLB flush, asynchronously from the CPU. > > > > And I think the answer about ASID is easy (on current hw).. it must be zero[*]. > > Using ASID zero is really bad, because it means that you will end up sharing > TLB entries with whichever device is using context bank 0. > > Is the SMMU only used by the GPU in your SoC? > yes, the snapdragon SoCs have two SMMU instances, one used by the GPU, where ASID0/cb0 is the gpu itself, and another cb is the GMU (basically power control for the gpu), and the second SMMU is everything else. BR, -R _______________________________________________ iommu mailing list iommu@lists.linux-foundation.org https://lists.linuxfoundation.org/mailman/listinfo/iommu