Re: [PATCH v3 4/4] arm64: dts: marvell: add SMMU support

[Marcin Wojtas <mw@semihalf.com>]

Hi Tomasz,


pt., 3 lip 2020 o 11:33 Tomasz Nowicki <tn@semihalf.com> napisał(a):
>
> On 03.07.2020 11:16, Robin Murphy wrote:
> > On 2020-07-02 21:16, Tomasz Nowicki wrote:
> >> From: Marcin Wojtas <mw@semihalf.com>
> >>
> >> Add IOMMU node for Marvell AP806 based SoCs together with platform
> >> and PCI device Stream ID mapping.
> >>
> >> Signed-off-by: Marcin Wojtas <mw@semihalf.com>
> >> Signed-off-by: Tomasz Nowicki <tn@semihalf.com>
> >> ---
> >>   arch/arm64/boot/dts/marvell/armada-8040.dtsi  | 36 +++++++++++++++++++
> >>   arch/arm64/boot/dts/marvell/armada-ap80x.dtsi | 17 +++++++++
> >>   2 files changed, 53 insertions(+)
> >>
> >> diff --git a/arch/arm64/boot/dts/marvell/armada-8040.dtsi
> >> b/arch/arm64/boot/dts/marvell/armada-8040.dtsi
> >> index 7699b19224c2..25c1df709f72 100644
> >> --- a/arch/arm64/boot/dts/marvell/armada-8040.dtsi
> >> +++ b/arch/arm64/boot/dts/marvell/armada-8040.dtsi
> >> @@ -23,3 +23,39 @@
> >>   &cp0_rtc {
> >>       status = "disabled";
> >>   };
> >> +
> >> +&cp0_usb3_0 {
> >> +    iommus = <&smmu 0x440>;
> >> +};
> >> +
> >> +&cp0_usb3_1 {
> >> +    iommus = <&smmu 0x441>;
> >> +};
> >> +
> >> +&cp0_sata0 {
> >> +    iommus = <&smmu 0x444>;
> >> +};
> >> +
> >> +&cp0_sdhci0 {
> >> +    iommus = <&smmu 0x445>;
> >> +};
> >> +
> >> +&cp1_sata0 {
> >> +    iommus = <&smmu 0x454>;
> >> +};
> >> +
> >> +&cp1_usb3_0 {
> >> +    iommus = <&smmu 0x450>;
> >> +};
> >> +
> >> +&cp1_usb3_1 {
> >> +    iommus = <&smmu 0x451>;
> >> +};
> >> +
> >> +&cp0_pcie0 {
> >> +    iommu-map =
> >> +        <0x0   &smmu 0x480 0x20>,
> >> +        <0x100 &smmu 0x4a0 0x20>,
> >> +        <0x200 &smmu 0x4c0 0x20>;
> >> +    iommu-map-mask = <0x031f>;
> >
> > Nice! I do like a good compressed mapping :D
> >
> >> +};
> >> diff --git a/arch/arm64/boot/dts/marvell/armada-ap80x.dtsi
> >> b/arch/arm64/boot/dts/marvell/armada-ap80x.dtsi
> >> index 7f9b9a647717..ded8b8082d79 100644
> >> --- a/arch/arm64/boot/dts/marvell/armada-ap80x.dtsi
> >> +++ b/arch/arm64/boot/dts/marvell/armada-ap80x.dtsi
> >> @@ -56,6 +56,23 @@
> >>               compatible = "simple-bus";
> >>               ranges = <0x0 0x0 0xf0000000 0x1000000>;
> >> +            smmu: iommu@5000000 {
> >> +                compatible = "marvell,ap806-smmu-500", "arm,mmu-500";
> >> +                reg = <0x100000 0x100000>;
> >> +                dma-coherent;
> >> +                #iommu-cells = <1>;
> >> +                #global-interrupts = <1>;
> >> +                interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
> >> +                         <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
> >> +                         <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
> >> +                         <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
> >> +                         <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
> >> +                         <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
> >> +                         <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
> >> +                         <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
> >> +                         <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
> >
> > I'd recommend you have the node disabled by default here, then
> > explicitly enable it in armada-8040.dtsi where you add the Stream IDs.
> > Otherwise it will also end up enabled for 8020, 70x0, etc. where
> > disable_bypass will then catastrophically break everything.
> >
>
> Good point! I will fix this.
>

In addition to above, I think it is worth defining the stream ID's for
Armada 7040 and CN913x SoCs.

Best regards,
Marcin
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