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Mon, 14 Dec 2020 01:33:06 -0800 (PST) Date: Mon, 14 Dec 2020 10:32:47 +0100 From: Jean-Philippe Brucker To: Krishna Reddy Subject: Re: [PATCH v10 10/13] iommu/arm-smmu-v3: Check for SVA features Message-ID: References: <20200918101852.582559-1-jean-philippe@linaro.org> <20200918101852.582559-11-jean-philippe@linaro.org> <753bcd76c21c4ea98ef1d4e492db01f4@huawei.com> <20200924101340.GC170808@myrica> <47b244b99f284790b82b2c0a968ba830@huawei.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: Cc: Sachin Nikam , "fenghua.yu@intel.com" , Yu-Huan Hsu , Suzuki K Poulose , "catalin.marinas@arm.com" , Alistair Popple , "robin.murphy@arm.com" , Pritesh Raithatha , Vikram Sethi , "linux-mm@kvack.org" , "iommu@lists.linux-foundation.org" , Jason Gunthorpe , "zhangfei.gao@linaro.org" , "will@kernel.org" , "linux-arm-kernel@lists.infradead.org" X-BeenThere: iommu@lists.linux-foundation.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: Development issues for Linux IOMMU support List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Errors-To: iommu-bounces@lists.linux-foundation.org Sender: "iommu" On Wed, Dec 09, 2020 at 07:49:09PM +0000, Krishna Reddy wrote: > Hi Jean, > > > Why is BTM mandated for SVA? I couldn't find this requirement in > > > SMMU spec (Sorry if I missed it or this got discussed earlier). But > > > if performance is the > > only concern here, > > > is it better just to allow it with a warning rather than limiting > > > SMMUs without > > BTM? > > > > It's a performance concern and requires to support multiple > > configurations, but the spec allows it. Are there SMMUs without BTM > > that need it? > > The Tegra Next Generation SOC uses arm-smmu-v3, but it doesn't have support for BTM. > Do you have plan to get your earlier patch to handle invalidate notifications into upstream sometime soon? > Can the dependency on BTM be relaxed with the patch? > > PATCH v9 13/13] iommu/arm-smmu-v3: Hook up ATC invalidation to mm ops > https://www.spinics.net/lists/arm-kernel/msg825099.html This patch (which should be in 5.11) only takes care of sending ATC invalidations to PCIe endpoints. With this, BTM is still required to invalidate SMMU TLBs. However we could enable command-queue invalidation when ARM_SMMU_FEAT_BTM isn't set. Invalidations are still a relatively rare event so it may not be outrageously slow. I can add a patch to my tree if you have hardware to test. This could also be a first step for enabling SVA on other systems as well, because I'm not finding time to work on BTM at the moment (requires pinning VMIDs in KVM). Thanks, Jean _______________________________________________ iommu mailing list iommu@lists.linux-foundation.org https://lists.linuxfoundation.org/mailman/listinfo/iommu