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b=dxHl6+nM9fiv/hXYlyZZ3HNmcwhJGsmIM15ResGd1qZBW0fV/Ta21Gq+3gU3g/tW2qFaZ0 Br2vzqpHdTwPQrXKwRr2ezUbMGxDIr1K48pcmBcD00AZOYXWeD02hz7VpVPaP09sBnzC5L s9pzxrjS4LSiGQfZ0keyE3S+hNYYEdk= Received: from mimecast-mx01.redhat.com (mimecast-mx01.redhat.com [209.132.183.4]) (Using TLS) by relay.mimecast.com with ESMTP id us-mta-8-2eFf2ebaO0eviYtmoxw0AA-1; Thu, 02 Jul 2020 03:16:26 -0400 X-MC-Unique: 2eFf2ebaO0eviYtmoxw0AA-1 Received: from smtp.corp.redhat.com (int-mx07.intmail.prod.int.phx2.redhat.com [10.5.11.22]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx01.redhat.com (Postfix) with ESMTPS id 1751F18A8220; Thu, 2 Jul 2020 07:16:25 +0000 (UTC) Received: from [10.36.112.70] (ovpn-112-70.ams2.redhat.com [10.36.112.70]) by smtp.corp.redhat.com (Postfix) with ESMTPS id AE7CA1002388; Thu, 2 Jul 2020 07:16:22 +0000 (UTC) Subject: Re: [PATCH v3 3/7] iommu/vt-d: Fix PASID devTLB invalidation To: Jacob Pan , iommu@lists.linux-foundation.org, LKML , Lu Baolu , Joerg Roedel , David Woodhouse References: <1593617636-79385-1-git-send-email-jacob.jun.pan@linux.intel.com> <1593617636-79385-4-git-send-email-jacob.jun.pan@linux.intel.com> From: Auger Eric Message-ID: Date: Thu, 2 Jul 2020 09:16:21 +0200 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.5.0 MIME-Version: 1.0 In-Reply-To: <1593617636-79385-4-git-send-email-jacob.jun.pan@linux.intel.com> Content-Language: en-US X-Scanned-By: MIMEDefang 2.84 on 10.5.11.22 Cc: "Tian, Kevin" , Raj Ashok X-BeenThere: iommu@lists.linux-foundation.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: Development issues for Linux IOMMU support List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Errors-To: iommu-bounces@lists.linux-foundation.org Sender: "iommu" Hi Jacob, On 7/1/20 5:33 PM, Jacob Pan wrote: > DevTLB flush can be used for both DMA request with and without PASIDs. > The former uses PASID#0 (RID2PASID), latter uses non-zero PASID for SVA > usage. > > This patch adds a check for PASID value such that devTLB flush with > PASID is used for SVA case. This is more efficient in that multiple > PASIDs can be used by a single device, when tearing down a PASID entry > we shall flush only the devTLB specific to a PASID. > > Fixes: 6f7db75e1c46 ("iommu/vt-d: Add second level page table") > Signed-off-by: Jacob Pan Reviewed-by: Eric Auger Thanks Eric > --- > drivers/iommu/intel/pasid.c | 11 ++++++++++- > 1 file changed, 10 insertions(+), 1 deletion(-) > > diff --git a/drivers/iommu/intel/pasid.c b/drivers/iommu/intel/pasid.c > index c81f0f17c6ba..fa0154cce537 100644 > --- a/drivers/iommu/intel/pasid.c > +++ b/drivers/iommu/intel/pasid.c > @@ -486,7 +486,16 @@ devtlb_invalidation_with_pasid(struct intel_iommu *iommu, > qdep = info->ats_qdep; > pfsid = info->pfsid; > > - qi_flush_dev_iotlb(iommu, sid, pfsid, qdep, 0, 64 - VTD_PAGE_SHIFT); > + /* > + * When PASID 0 is used, it indicates RID2PASID(DMA request w/o PASID), > + * devTLB flush w/o PASID should be used. For non-zero PASID under > + * SVA usage, device could do DMA with multiple PASIDs. It is more > + * efficient to flush devTLB specific to the PASID. > + */ > + if (pasid == PASID_RID2PASID) > + qi_flush_dev_iotlb(iommu, sid, pfsid, qdep, 0, 64 - VTD_PAGE_SHIFT); > + else > + qi_flush_dev_iotlb_pasid(iommu, sid, pfsid, pasid, qdep, 0, 64 - VTD_PAGE_SHIFT); > } > > void intel_pasid_tear_down_entry(struct intel_iommu *iommu, struct device *dev, > _______________________________________________ iommu mailing list iommu@lists.linux-foundation.org https://lists.linuxfoundation.org/mailman/listinfo/iommu