From: Auger Eric <eric.auger@redhat.com>
To: Jacob Pan <jacob.jun.pan@linux.intel.com>,
Lu Baolu <baolu.lu@linux.intel.com>,
iommu@lists.linux-foundation.org,
LKML <linux-kernel@vger.kernel.org>,
Joerg Roedel <joro@8bytes.org>,
David Woodhouse <dwmw2@infradead.org>,
Alex Williamson <alex.williamson@redhat.com>,
Jean-Philippe Brucker <jean-philippe@linaro.com>
Cc: "Tian, Kevin" <kevin.tian@intel.com>,
Raj Ashok <ashok.raj@intel.com>,
Jonathan Cameron <jic23@kernel.org>
Subject: Re: [PATCH V10 07/11] iommu/vt-d: Support flushing more translation cache types
Date: Fri, 27 Mar 2020 15:46:23 +0100 [thread overview]
Message-ID: <c90fafad-253a-b2f5-2a6c-87bc319edd02@redhat.com> (raw)
In-Reply-To: <1584746861-76386-8-git-send-email-jacob.jun.pan@linux.intel.com>
Hi Jacob,
On 3/21/20 12:27 AM, Jacob Pan wrote:
> When Shared Virtual Memory is exposed to a guest via vIOMMU, scalable
> IOTLB invalidation may be passed down from outside IOMMU subsystems.
> This patch adds invalidation functions that can be used for additional
> translation cache types.
>
> Signed-off-by: Jacob Pan <jacob.jun.pan@linux.intel.com>
>
> ---
> v9 -> v10:
> Fix off by 1 in pasid device iotlb flush
>
> Address v7 missed review from Eric
>
> ---
> ---
> drivers/iommu/dmar.c | 36 ++++++++++++++++++++++++++++++++++++
> drivers/iommu/intel-pasid.c | 3 ++-
> include/linux/intel-iommu.h | 20 ++++++++++++++++----
> 3 files changed, 54 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/iommu/dmar.c b/drivers/iommu/dmar.c
> index f77dae7ba7d4..4d6b7b5b37ee 100644
> --- a/drivers/iommu/dmar.c
> +++ b/drivers/iommu/dmar.c
> @@ -1421,6 +1421,42 @@ void qi_flush_piotlb(struct intel_iommu *iommu, u16 did, u32 pasid, u64 addr,
> qi_submit_sync(&desc, iommu);
> }
>
> +/* PASID-based device IOTLB Invalidate */
> +void qi_flush_dev_iotlb_pasid(struct intel_iommu *iommu, u16 sid, u16 pfsid,
> + u32 pasid, u16 qdep, u64 addr, unsigned size_order, u64 granu)
> +{
> + unsigned long mask = 1UL << (VTD_PAGE_SHIFT + size_order - 1);
> + struct qi_desc desc = {.qw2 = 0, .qw3 = 0};
> +
> + desc.qw0 = QI_DEV_EIOTLB_PASID(pasid) | QI_DEV_EIOTLB_SID(sid) |
> + QI_DEV_EIOTLB_QDEP(qdep) | QI_DEIOTLB_TYPE |
> + QI_DEV_IOTLB_PFSID(pfsid);
> + desc.qw1 = QI_DEV_EIOTLB_GLOB(granu);
> +
> + /*
> + * If S bit is 0, we only flush a single page. If S bit is set,
> + * The least significant zero bit indicates the invalidation address
> + * range. VT-d spec 6.5.2.6.
> + * e.g. address bit 12[0] indicates 8KB, 13[0] indicates 16KB.
> + * size order = 0 is PAGE_SIZE 4KB
> + * Max Invs Pending (MIP) is set to 0 for now until we have DIT in
> + * ECAP.
> + */
> + desc.qw1 |= addr & ~mask;
> + if (size_order)
> + desc.qw1 |= QI_DEV_EIOTLB_SIZE;
> +
> + qi_submit_sync(&desc, iommu);
> +}
> +
> +void qi_flush_pasid_cache(struct intel_iommu *iommu, u16 did, u64 granu, int pasid)
> +{
> + struct qi_desc desc = {.qw1 = 0, .qw2 = 0, .qw3 = 0};
> +
> + desc.qw0 = QI_PC_PASID(pasid) | QI_PC_DID(did) | QI_PC_GRAN(granu) | QI_PC_TYPE;
> + qi_submit_sync(&desc, iommu);
> +}
> +
> /*
> * Disable Queued Invalidation interface.
> */
> diff --git a/drivers/iommu/intel-pasid.c b/drivers/iommu/intel-pasid.c
> index 10c7856afc6b..9f6d07410722 100644
> --- a/drivers/iommu/intel-pasid.c
> +++ b/drivers/iommu/intel-pasid.c
> @@ -435,7 +435,8 @@ pasid_cache_invalidation_with_pasid(struct intel_iommu *iommu,
> {
> struct qi_desc desc;
>
> - desc.qw0 = QI_PC_DID(did) | QI_PC_PASID_SEL | QI_PC_PASID(pasid);
> + desc.qw0 = QI_PC_DID(did) | QI_PC_GRAN(QI_PC_PASID_SEL) |
> + QI_PC_PASID(pasid) | QI_PC_TYPE;
Just a nit, this fix is not documented in the commit message.
Besides
Reviewed-by: Eric Auger <eric.auger@redhat.com>
Thanks
Eric
> desc.qw1 = 0;
> desc.qw2 = 0;
> desc.qw3 = 0;
> diff --git a/include/linux/intel-iommu.h b/include/linux/intel-iommu.h
> index 85b05120940e..43539713b3b3 100644
> --- a/include/linux/intel-iommu.h
> +++ b/include/linux/intel-iommu.h
> @@ -334,7 +334,7 @@ enum {
> #define QI_IOTLB_GRAN(gran) (((u64)gran) >> (DMA_TLB_FLUSH_GRANU_OFFSET-4))
> #define QI_IOTLB_ADDR(addr) (((u64)addr) & VTD_PAGE_MASK)
> #define QI_IOTLB_IH(ih) (((u64)ih) << 6)
> -#define QI_IOTLB_AM(am) (((u8)am))
> +#define QI_IOTLB_AM(am) (((u8)am) & 0x3f)
>
> #define QI_CC_FM(fm) (((u64)fm) << 48)
> #define QI_CC_SID(sid) (((u64)sid) << 32)
> @@ -353,16 +353,21 @@ enum {
> #define QI_PC_DID(did) (((u64)did) << 16)
> #define QI_PC_GRAN(gran) (((u64)gran) << 4)
>
> -#define QI_PC_ALL_PASIDS (QI_PC_TYPE | QI_PC_GRAN(0))
> -#define QI_PC_PASID_SEL (QI_PC_TYPE | QI_PC_GRAN(1))
> +/* PASID cache invalidation granu */
> +#define QI_PC_ALL_PASIDS 0
> +#define QI_PC_PASID_SEL 1
>
> #define QI_EIOTLB_ADDR(addr) ((u64)(addr) & VTD_PAGE_MASK)
> #define QI_EIOTLB_IH(ih) (((u64)ih) << 6)
> -#define QI_EIOTLB_AM(am) (((u64)am))
> +#define QI_EIOTLB_AM(am) (((u64)am) & 0x3f)
> #define QI_EIOTLB_PASID(pasid) (((u64)pasid) << 32)
> #define QI_EIOTLB_DID(did) (((u64)did) << 16)
> #define QI_EIOTLB_GRAN(gran) (((u64)gran) << 4)
>
> +/* QI Dev-IOTLB inv granu */
> +#define QI_DEV_IOTLB_GRAN_ALL 1
> +#define QI_DEV_IOTLB_GRAN_PASID_SEL 0> +
> #define QI_DEV_EIOTLB_ADDR(a) ((u64)(a) & VTD_PAGE_MASK)
> #define QI_DEV_EIOTLB_SIZE (((u64)1) << 11)
> #define QI_DEV_EIOTLB_GLOB(g) ((u64)g)
> @@ -662,8 +667,15 @@ extern void qi_flush_iotlb(struct intel_iommu *iommu, u16 did, u64 addr,
> unsigned int size_order, u64 type);
> extern void qi_flush_dev_iotlb(struct intel_iommu *iommu, u16 sid, u16 pfsid,
> u16 qdep, u64 addr, unsigned mask);
> +
> void qi_flush_piotlb(struct intel_iommu *iommu, u16 did, u32 pasid, u64 addr,
> unsigned long npages, bool ih);
> +
> +extern void qi_flush_dev_iotlb_pasid(struct intel_iommu *iommu, u16 sid, u16 pfsid,
> + u32 pasid, u16 qdep, u64 addr, unsigned size_order, u64 granu);
> +
> +extern void qi_flush_pasid_cache(struct intel_iommu *iommu, u16 did, u64 granu, int pasid);
> +
> extern int qi_submit_sync(struct qi_desc *desc, struct intel_iommu *iommu);
>
> extern int dmar_ir_support(void);
>
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next prev parent reply other threads:[~2020-03-27 14:46 UTC|newest]
Thread overview: 67+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-03-20 23:27 [PATCH V10 00/11] Nested Shared Virtual Address (SVA) VT-d support Jacob Pan
2020-03-20 23:27 ` [PATCH V10 01/11] iommu/vt-d: Move domain helper to header Jacob Pan
2020-03-27 11:48 ` Tian, Kevin
2020-03-20 23:27 ` [PATCH V10 02/11] iommu/uapi: Define a mask for bind data Jacob Pan
2020-03-22 1:29 ` Lu Baolu
2020-03-23 19:37 ` Jacob Pan
2020-03-24 1:50 ` Lu Baolu
2020-03-27 11:50 ` Tian, Kevin
2020-03-27 14:13 ` Auger Eric
2020-03-20 23:27 ` [PATCH V10 03/11] iommu/vt-d: Add a helper function to skip agaw Jacob Pan
2020-03-27 11:53 ` Tian, Kevin
2020-03-29 7:20 ` Lu Baolu
2020-03-30 17:50 ` Jacob Pan
2020-03-20 23:27 ` [PATCH V10 04/11] iommu/vt-d: Use helper function to skip agaw for SL Jacob Pan
2020-03-27 11:55 ` Tian, Kevin
2020-03-27 16:05 ` Auger Eric
2020-03-29 7:35 ` Lu Baolu
2020-03-20 23:27 ` [PATCH V10 05/11] iommu/vt-d: Add nested translation helper function Jacob Pan
2020-03-27 12:21 ` Tian, Kevin
2020-03-29 8:03 ` Lu Baolu
2020-03-30 18:21 ` Jacob Pan
2020-03-31 3:36 ` Tian, Kevin
2020-03-29 11:35 ` Auger Eric
2020-04-01 20:06 ` Jacob Pan
2020-03-20 23:27 ` [PATCH V10 06/11] iommu/vt-d: Add bind guest PASID support Jacob Pan
2020-03-28 8:02 ` Tian, Kevin
2020-03-30 20:51 ` Jacob Pan
2020-03-31 3:43 ` Tian, Kevin
2020-04-01 17:13 ` Jacob Pan
2020-03-29 13:40 ` Auger Eric
2020-03-30 22:53 ` Jacob Pan
2020-03-20 23:27 ` [PATCH V10 07/11] iommu/vt-d: Support flushing more translation cache types Jacob Pan
2020-03-27 14:46 ` Auger Eric [this message]
2020-03-30 23:28 ` Jacob Pan
2020-03-31 16:13 ` Jacob Pan
2020-03-31 16:15 ` Auger Eric
2020-03-20 23:27 ` [PATCH V10 08/11] iommu/vt-d: Add svm/sva invalidate function Jacob Pan
2020-03-28 10:01 ` Tian, Kevin
2020-03-29 15:34 ` Auger Eric
2020-03-31 2:49 ` Tian, Kevin
2020-03-31 20:58 ` Jacob Pan
2020-04-01 6:29 ` Tian, Kevin
2020-04-01 7:13 ` Liu, Yi L
2020-04-01 7:32 ` Auger Eric
2020-04-01 16:05 ` Jacob Pan
2020-04-02 15:54 ` Jacob Pan
2020-03-29 16:05 ` Auger Eric
2020-03-31 3:34 ` Tian, Kevin
2020-03-31 21:07 ` Jacob Pan
2020-04-01 6:32 ` Tian, Kevin
2020-03-31 18:13 ` Jacob Pan
2020-04-01 6:24 ` Tian, Kevin
2020-04-01 6:57 ` Liu, Yi L
2020-04-01 16:03 ` Jacob Pan
2020-03-29 16:05 ` Auger Eric
2020-03-31 22:28 ` Jacob Pan
2020-03-20 23:27 ` [PATCH V10 09/11] iommu/vt-d: Cache virtual command capability register Jacob Pan
2020-03-28 10:04 ` Tian, Kevin
2020-03-31 22:33 ` Jacob Pan
2020-03-20 23:27 ` [PATCH V10 10/11] iommu/vt-d: Enlightened PASID allocation Jacob Pan
2020-03-28 10:08 ` Tian, Kevin
2020-03-31 22:37 ` Jacob Pan
2020-03-20 23:27 ` [PATCH V10 11/11] iommu/vt-d: Add custom allocator for IOASID Jacob Pan
2020-03-28 10:22 ` Tian, Kevin
2020-04-01 15:47 ` Jacob Pan
2020-04-02 2:18 ` Tian, Kevin
2020-04-02 20:28 ` Jacob Pan
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