Re: arm-smmu-v3 high cpu usage for NVMe

[John Garry <john.garry@huawei.com>]

On 20/03/2020 16:33, Marc Zyngier wrote:
>> JFYI, I've been playing for "perf annotate" today and it's giving
>> strange results for my NVMe testing. So "report" looks somewhat sane,
>> if not a worryingly high % for arm_smmu_cmdq_issue_cmdlist():
>>
>>
>>     55.39%  irq/342-nvme0q1  [kernel.kallsyms]  [k] 
>> arm_smmu_cmdq_issue_cmdlist
>>      9.74%  irq/342-nvme0q1  [kernel.kallsyms]  [k] 
>> _raw_spin_unlock_irqrestore
>>      2.02%  irq/342-nvme0q1  [kernel.kallsyms]  [k] nvme_irq
>>      1.86%  irq/342-nvme0q1  [kernel.kallsyms]  [k] fput_many
>>      1.73%  irq/342-nvme0q1  [kernel.kallsyms]  [k]
>> arm_smmu_atc_inv_domain.constprop.42
>>      1.67%  irq/342-nvme0q1  [kernel.kallsyms]  [k] __arm_lpae_unmap
>>      1.49%  irq/342-nvme0q1  [kernel.kallsyms]  [k] aio_complete_rw
>>
>> But "annotate" consistently tells me that a specific instruction
>> consumes ~99% of the load for the enqueue function:
>>
>>          :                      /* 5. If we are inserting a CMD_SYNC,
>> we must wait for it to complete */
>>          :                      if (sync) {
>>     0.00 :   ffff80001071c948:       ldr     w0, [x29, #108]
>>          :                      int ret = 0;
>>     0.00 :   ffff80001071c94c:       mov     w24, #0x0      // #0
>>          :                      if (sync) {
>>     0.00 :   ffff80001071c950:       cbnz    w0, ffff80001071c990
>> <arm_smmu_cmdq_issue_cmdlist+0x420>
>>          :                      arch_local_irq_restore():
>>     0.00 :   ffff80001071c954:       msr     daif, x21
>>          :                      arm_smmu_cmdq_issue_cmdlist():
>>          :                      }
>>          :                      }
>>          :
>>          :                      local_irq_restore(flags);
>>          :                      return ret;
>>          :                      }
>>    99.51 :   ffff80001071c958:       adrp    x0, ffff800011909000
>> <page_wait_table+0x14c0>
> 

Hi Marc,

> This is likely the side effect of the re-enabling of interrupts (msr 
> daif, x21)
> on the previous instruction which causes the perf interrupt to fire 
> right after.

ok, makes sense.

> 
> Time to enable pseudo-NMIs in the PMUv3 driver...
> 

Do you know if there is any plan for this?

In the meantime, maybe I can do some trickery by putting the 
local_irq_restore() in a separate function, outside 
arm_smmu_cmdq_issue_cmdlist(), to get a fair profile for that same function.

Cheers,
John
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