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charset="us-ascii"; Format="flowed" Errors-To: iommu-bounces@lists.linux-foundation.org Sender: "iommu" Hi Joerg, Do you have any concerns regarding this patch? Thanks, Suravee On 10/15/20 9:50 AM, Suravee Suthikulpanit wrote: > Certain device drivers allocate IO queues on a per-cpu basis. > On AMD EPYC platform, which can support up-to 256 cpu threads, > this can exceed the current MAX_IRQ_PER_TABLE limit of 256, > and result in the error message: > > AMD-Vi: Failed to allocate IRTE > > This has been observed with certain NVME devices. > > AMD IOMMU hardware can actually support upto 512 interrupt > remapping table entries. Therefore, update the driver to > match the hardware limit. > > Please note that this also increases the size of interrupt remapping > table to 8KB per device when using the 128-bit IRTE format. > > Signed-off-by: Suravee Suthikulpanit > --- > drivers/iommu/amd/amd_iommu_types.h | 6 +++++- > 1 file changed, 5 insertions(+), 1 deletion(-) > > diff --git a/drivers/iommu/amd/amd_iommu_types.h b/drivers/iommu/amd/amd_iommu_types.h > index 30a5d412255a..427484c45589 100644 > --- a/drivers/iommu/amd/amd_iommu_types.h > +++ b/drivers/iommu/amd/amd_iommu_types.h > @@ -406,7 +406,11 @@ extern bool amd_iommu_np_cache; > /* Only true if all IOMMUs support device IOTLBs */ > extern bool amd_iommu_iotlb_sup; > > -#define MAX_IRQS_PER_TABLE 256 > +/* > + * AMD IOMMU hardware only support 512 IRTEs despite > + * the architectural limitation of 2048 entries. > + */ > +#define MAX_IRQS_PER_TABLE 512 > #define IRQ_TABLE_ALIGNMENT 128 > > struct irq_remap_table { > _______________________________________________ iommu mailing list iommu@lists.linux-foundation.org https://lists.linuxfoundation.org/mailman/listinfo/iommu