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[83.9.29.96]) by smtp.gmail.com with ESMTPSA id l7-20020ac25547000000b004f6150e08a6sm1133630lfk.288.2023.06.05.11.17.27 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 05 Jun 2023 11:17:29 -0700 (PDT) Message-ID: Date: Mon, 5 Jun 2023 20:17:27 +0200 Precedence: bulk X-Mailing-List: iommu@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.11.2 Subject: Re: [PATCH v2 08/10] arm64: dts: qcom: Add QUPv3 UART console node for SDX75 Content-Language: en-US To: Rohit Agarwal , agross@kernel.org, andersson@kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org, rafael@kernel.org, viresh.kumar@linaro.org, tglx@linutronix.de, maz@kernel.org, will@kernel.org, robin.murphy@arm.com, joro@8bytes.org, mani@kernel.org, robimarko@gmail.com Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, iommu@lists.linux.dev References: <1685982557-28326-1-git-send-email-quic_rohiagar@quicinc.com> <1685982557-28326-9-git-send-email-quic_rohiagar@quicinc.com> From: Konrad Dybcio In-Reply-To: <1685982557-28326-9-git-send-email-quic_rohiagar@quicinc.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit On 5.06.2023 18:29, Rohit Agarwal wrote: > Add the debug uart console node in devicetree. > > Signed-off-by: Rohit Agarwal > --- > arch/arm64/boot/dts/qcom/sdx75.dtsi | 49 +++++++++++++++++++++++++++++++++++++ > 1 file changed, 49 insertions(+) > > diff --git a/arch/arm64/boot/dts/qcom/sdx75.dtsi b/arch/arm64/boot/dts/qcom/sdx75.dtsi > index f83eef8..47170ae 100644 > --- a/arch/arm64/boot/dts/qcom/sdx75.dtsi > +++ b/arch/arm64/boot/dts/qcom/sdx75.dtsi > @@ -385,6 +385,34 @@ > #power-domain-cells = <1>; > }; > > + qupv3_id_0: geniqup@9c0000 { > + compatible = "qcom,geni-se-qup"; > + reg = <0x0 0x009c0000 0x0 0x2000>; > + clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, > + <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; > + clock-names = "m-ahb", > + "s-ahb"; > + iommus = <&apps_smmu 0xe3 0x0>; > + #address-cells = <2>; > + #size-cells = <2>; > + ranges; > + status = "disabled"; > + > + uart1: serial@984000 { > + compatible = "qcom,geni-debug-uart"; > + reg = <0x0 0x00984000 0x0 0x4000>; > + clock-names = "se"; > + clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; > + interrupts = ; > + pinctrl-0 = <&qupv3_se1_2uart_tx_active>, > + <&qupv3_se1_2uart_rx_active>; > + pinctrl-1 = <&qupv3_se1_2uart_sleep>; > + pinctrl-names = "default", > + "sleep"; > + status = "disabled"; > + }; > + }; > + > tcsr_mutex: hwlock@1f40000 { > compatible = "qcom,tcsr-mutex"; > reg = <0x0 0x01f40000 0x0 0x40000>; > @@ -413,6 +441,27 @@ > interrupt-controller; > #interrupt-cells = <2>; > wakeup-parent = <&pdc>; > + > + qupv3_se1_2uart_tx_active: qupv3-se1-2uart-tx-active-state { > + pins = "gpio12"; > + function = "qup_se1_l2_mira"; > + drive-strength= <2>; > + bias-disable; > + }; You can bunch these two up like this: qupv3_se1_2uart_active: qup.... { tx { pins = ... foo = ... }; rx { pins = ... bar = ... }; }; Konrad > + > + qupv3_se1_2uart_rx_active: qupv3-se1-2uart-rx-active-state { > + pins = "gpio13"; > + function = "qup_se1_l3_mira"; > + drive-strength= <2>; > + bias-disable; > + }; > + > + qupv3_se1_2uart_sleep: qupv3-se1-2uart-sleep-state { > + pins = "gpio12", "gpio13"; > + function = "gpio"; > + drive-strength = <2>; > + bias-pull-down; > + }; > }; > > apps_smmu: iommu@15000000 {