From: Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org>
To: Robin Murphy <robin.murphy@arm.com>,
Will Deacon <will@kernel.org>, Joerg Roedel <joro@8bytes.org>,
Jordan Crouse <jcrouse@codeaurora.org>,
Rob Clark <robdclark@gmail.com>
Cc: freedreno@lists.freedesktop.org, David Airlie <airlied@linux.ie>,
linux-arm-msm@vger.kernel.org,
Sharat Masetty <smasetty@codeaurora.org>,
linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org,
Akhil P Oommen <akhilpo@codeaurora.org>,
iommu@lists.linux-foundation.org,
Matthias Kaehlcke <mka@chromium.org>,
"Kristian H . Kristensen" <hoegsberg@google.com>,
Daniel Vetter <daniel@ffwll.ch>,
Stephen Boyd <swboyd@chromium.org>, Sean Paul <sean@poorly.run>,
linux-arm-kernel@lists.infradead.org,
Emil Velikov <emil.velikov@collabora.com>
Subject: [PATCHv3 2/7] iommu/io-pgtable-arm: Add support to use system cache
Date: Mon, 29 Jun 2020 21:22:45 +0530 [thread overview]
Message-ID: <e167bbb8625c0ab6701f2b48416b88d260bd0ab0.1593344119.git.saiprakash.ranjan@codeaurora.org> (raw)
In-Reply-To: <cover.1593344119.git.saiprakash.ranjan@codeaurora.org>
Add a quirk IO_PGTABLE_QUIRK_SYS_CACHE to override the
attributes set in TCR for the page table walker when
using system cache.
Signed-off-by: Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org>
---
drivers/iommu/io-pgtable-arm.c | 7 ++++++-
include/linux/io-pgtable.h | 4 ++++
2 files changed, 10 insertions(+), 1 deletion(-)
diff --git a/drivers/iommu/io-pgtable-arm.c b/drivers/iommu/io-pgtable-arm.c
index 04fbd4bf0ff9..0a6cb82fd98a 100644
--- a/drivers/iommu/io-pgtable-arm.c
+++ b/drivers/iommu/io-pgtable-arm.c
@@ -792,7 +792,8 @@ arm_64_lpae_alloc_pgtable_s1(struct io_pgtable_cfg *cfg, void *cookie)
if (cfg->quirks & ~(IO_PGTABLE_QUIRK_ARM_NS |
IO_PGTABLE_QUIRK_NON_STRICT |
- IO_PGTABLE_QUIRK_ARM_TTBR1))
+ IO_PGTABLE_QUIRK_ARM_TTBR1 |
+ IO_PGTABLE_QUIRK_SYS_CACHE))
return NULL;
data = arm_lpae_alloc_pgtable(cfg);
@@ -804,6 +805,10 @@ arm_64_lpae_alloc_pgtable_s1(struct io_pgtable_cfg *cfg, void *cookie)
tcr->sh = ARM_LPAE_TCR_SH_IS;
tcr->irgn = ARM_LPAE_TCR_RGN_WBWA;
tcr->orgn = ARM_LPAE_TCR_RGN_WBWA;
+ } else if (cfg->quirks & IO_PGTABLE_QUIRK_SYS_CACHE) {
+ tcr->sh = ARM_LPAE_TCR_SH_OS;
+ tcr->irgn = ARM_LPAE_TCR_RGN_NC;
+ tcr->orgn = ARM_LPAE_TCR_RGN_WBWA;
} else {
tcr->sh = ARM_LPAE_TCR_SH_OS;
tcr->irgn = ARM_LPAE_TCR_RGN_NC;
diff --git a/include/linux/io-pgtable.h b/include/linux/io-pgtable.h
index bbed1d3925ba..23114b3fe2a5 100644
--- a/include/linux/io-pgtable.h
+++ b/include/linux/io-pgtable.h
@@ -86,6 +86,9 @@ struct io_pgtable_cfg {
*
* IO_PGTABLE_QUIRK_ARM_TTBR1: (ARM LPAE format) Configure the table
* for use in the upper half of a split address space.
+ *
+ * IO_PGTABLE_QUIRK_SYS_CACHE: Override the attributes set in TCR for
+ * the page table walker when using system cache.
*/
#define IO_PGTABLE_QUIRK_ARM_NS BIT(0)
#define IO_PGTABLE_QUIRK_NO_PERMS BIT(1)
@@ -93,6 +96,7 @@ struct io_pgtable_cfg {
#define IO_PGTABLE_QUIRK_ARM_MTK_EXT BIT(3)
#define IO_PGTABLE_QUIRK_NON_STRICT BIT(4)
#define IO_PGTABLE_QUIRK_ARM_TTBR1 BIT(5)
+ #define IO_PGTABLE_QUIRK_SYS_CACHE BIT(6)
unsigned long quirks;
unsigned long pgsize_bitmap;
unsigned int ias;
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation
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iommu@lists.linux-foundation.org
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next prev parent reply other threads:[~2020-06-29 15:53 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-06-29 15:52 [PATCHv3 0/7] System Cache support for GPU and required SMMU support Sai Prakash Ranjan
2020-06-29 15:52 ` [PATCHv3 1/7] iommu/arm-smmu: Add a init_context_bank implementation hook Sai Prakash Ranjan
2020-06-29 15:52 ` Sai Prakash Ranjan [this message]
2020-06-29 15:52 ` [PATCHv3 3/7] iommu/arm-smmu: Add domain attribute for system cache Sai Prakash Ranjan
2020-06-29 15:52 ` [PATCHv3 4/7] iommu: arm-smmu-impl: Remove unwanted extra blank lines Sai Prakash Ranjan
2020-06-29 15:52 ` [PATCHv3 5/7] iommu: arm-smmu-impl: Convert to use of_match_node() for qcom impl Sai Prakash Ranjan
2020-06-29 15:52 ` [PATCHv3 6/7] drm/msm: rearrange the gpu_rmw() function Sai Prakash Ranjan
2020-06-29 15:52 ` [PATCHv3 7/7] drm/msm/a6xx: Add support for using system cache(LLC) Sai Prakash Ranjan
2020-07-03 13:37 ` Will Deacon
2020-07-03 14:53 ` Sai Prakash Ranjan
2020-07-03 15:40 ` Will Deacon
2020-07-03 16:04 ` Rob Clark
2020-07-03 16:59 ` Sai Prakash Ranjan
2020-07-09 16:13 ` Jordan Crouse
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