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From: Auger Eric <eric.auger@redhat.com>
To: Jacob Pan <jacob.jun.pan@linux.intel.com>,
	iommu@lists.linux-foundation.org,
	LKML <linux-kernel@vger.kernel.org>,
	Lu Baolu <baolu.lu@linux.intel.com>,
	Joerg Roedel <joro@8bytes.org>,
	David Woodhouse <dwmw2@infradead.org>
Cc: "Tian, Kevin" <kevin.tian@intel.com>, Raj Ashok <ashok.raj@intel.com>
Subject: Re: [PATCH v3 2/7] iommu/vt-d: Remove global page support in devTLB flush
Date: Thu, 2 Jul 2020 09:16:22 +0200	[thread overview]
Message-ID: <e4b05249-bf1b-4d27-f76b-90a80f8586b2@redhat.com> (raw)
In-Reply-To: <1593617636-79385-3-git-send-email-jacob.jun.pan@linux.intel.com>

Hi Jacob,

On 7/1/20 5:33 PM, Jacob Pan wrote:
> Global pages support is removed from VT-d spec 3.0 for dev TLB
> invalidation. This patch is to remove the bits for vSVA. Similar change
> already made for the native SVA. See the link below.
> 
> Link: https://lkml.org/lkml/2019/8/26/651
> Acked-by: Lu Baolu <baolu.lu@linux.intel.com>
> Signed-off-by: Jacob Pan <jacob.jun.pan@linux.intel.com>
> ---
>  drivers/iommu/intel/dmar.c  | 4 +---
>  drivers/iommu/intel/iommu.c | 4 ++--
>  include/linux/intel-iommu.h | 3 +--
>  3 files changed, 4 insertions(+), 7 deletions(-)
> 
> diff --git a/drivers/iommu/intel/dmar.c b/drivers/iommu/intel/dmar.c
> index cc46dff98fa0..d9f973fa1190 100644
> --- a/drivers/iommu/intel/dmar.c
> +++ b/drivers/iommu/intel/dmar.c
> @@ -1437,8 +1437,7 @@ void qi_flush_piotlb(struct intel_iommu *iommu, u16 did, u32 pasid, u64 addr,
>  
>  /* PASID-based device IOTLB Invalidate */
>  void qi_flush_dev_iotlb_pasid(struct intel_iommu *iommu, u16 sid, u16 pfsid,
> -			      u32 pasid,  u16 qdep, u64 addr,
> -			      unsigned int size_order, u64 granu)
> +			      u32 pasid,  u16 qdep, u64 addr, unsigned int size_order)
>  {
>  	unsigned long mask = 1UL << (VTD_PAGE_SHIFT + size_order - 1);
>  	struct qi_desc desc = {.qw1 = 0, .qw2 = 0, .qw3 = 0};
> @@ -1446,7 +1445,6 @@ void qi_flush_dev_iotlb_pasid(struct intel_iommu *iommu, u16 sid, u16 pfsid,
>  	desc.qw0 = QI_DEV_EIOTLB_PASID(pasid) | QI_DEV_EIOTLB_SID(sid) |
>  		QI_DEV_EIOTLB_QDEP(qdep) | QI_DEIOTLB_TYPE |
>  		QI_DEV_IOTLB_PFSID(pfsid);
> -	desc.qw1 = QI_DEV_EIOTLB_GLOB(granu);
nit:

you may simplify the init of .qw1 to
.qw1 = addr & ~mask

as you have
desc.qw1 |= addr & ~mask;

Besides
Reviewed-by: Eric Auger <eric.auger@redhat.com>

Thanks

Eric

>  
>  	/*
>  	 * If S bit is 0, we only flush a single page. If S bit is set,
> diff --git a/drivers/iommu/intel/iommu.c b/drivers/iommu/intel/iommu.c
> index 9129663a7406..96340da57075 100644
> --- a/drivers/iommu/intel/iommu.c
> +++ b/drivers/iommu/intel/iommu.c
> @@ -5466,7 +5466,7 @@ intel_iommu_sva_invalidate(struct iommu_domain *domain, struct device *dev,
>  						info->pfsid, pasid,
>  						info->ats_qdep,
>  						inv_info->addr_info.addr,
> -						size, granu);
> +						size);
>  			break;
>  		case IOMMU_CACHE_INV_TYPE_DEV_IOTLB:
>  			if (info->ats_enabled)
> @@ -5474,7 +5474,7 @@ intel_iommu_sva_invalidate(struct iommu_domain *domain, struct device *dev,
>  						info->pfsid, pasid,
>  						info->ats_qdep,
>  						inv_info->addr_info.addr,
> -						size, granu);
> +						size);
>  			else
>  				pr_warn_ratelimited("Passdown device IOTLB flush w/o ATS!\n");
>  			break;
> diff --git a/include/linux/intel-iommu.h b/include/linux/intel-iommu.h
> index 729386ca8122..9a6614880773 100644
> --- a/include/linux/intel-iommu.h
> +++ b/include/linux/intel-iommu.h
> @@ -380,7 +380,6 @@ enum {
>  
>  #define QI_DEV_EIOTLB_ADDR(a)	((u64)(a) & VTD_PAGE_MASK)
>  #define QI_DEV_EIOTLB_SIZE	(((u64)1) << 11)
> -#define QI_DEV_EIOTLB_GLOB(g)	((u64)(g) & 0x1)
>  #define QI_DEV_EIOTLB_PASID(p)	((u64)((p) & 0xfffff) << 32)
>  #define QI_DEV_EIOTLB_SID(sid)	((u64)((sid) & 0xffff) << 16)
>  #define QI_DEV_EIOTLB_QDEP(qd)	((u64)((qd) & 0x1f) << 4)
> @@ -704,7 +703,7 @@ void qi_flush_piotlb(struct intel_iommu *iommu, u16 did, u32 pasid, u64 addr,
>  
>  void qi_flush_dev_iotlb_pasid(struct intel_iommu *iommu, u16 sid, u16 pfsid,
>  			      u32 pasid, u16 qdep, u64 addr,
> -			      unsigned int size_order, u64 granu);
> +			      unsigned int size_order);
>  void qi_flush_pasid_cache(struct intel_iommu *iommu, u16 did, u64 granu,
>  			  int pasid);
>  
> 

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  reply	other threads:[~2020-07-02  7:16 UTC|newest]

Thread overview: 21+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-07-01 15:33 [PATCH v3 0/7] iommu/vt-d: Misc tweaks and fixes for vSVA Jacob Pan
2020-07-01 15:33 ` [PATCH v3 1/7] iommu/vt-d: Enforce PASID devTLB field mask Jacob Pan
2020-07-02  7:16   ` Auger Eric
2020-07-01 15:33 ` [PATCH v3 2/7] iommu/vt-d: Remove global page support in devTLB flush Jacob Pan
2020-07-02  7:16   ` Auger Eric [this message]
2020-07-06 23:58     ` Jacob Pan
2020-07-01 15:33 ` [PATCH v3 3/7] iommu/vt-d: Fix PASID devTLB invalidation Jacob Pan
2020-07-02  0:50   ` Lu Baolu
2020-07-02  7:16   ` Auger Eric
2020-07-01 15:33 ` [PATCH v3 4/7] iommu/vt-d: Handle non-page aligned address Jacob Pan
2020-07-02  7:50   ` Auger Eric
2020-07-06 23:28     ` Jacob Pan
2020-07-01 15:33 ` [PATCH v3 5/7] iommu/vt-d: Fix devTLB flush for vSVA Jacob Pan
2020-07-02  8:39   ` Auger Eric
2020-07-06 21:05     ` Jacob Pan
2020-07-01 15:33 ` [PATCH v3 6/7] iommu/vt-d: Warn on out-of-range invalidation address Jacob Pan
2020-07-02  0:55   ` Lu Baolu
2020-07-02  8:47   ` Auger Eric
2020-07-02 13:43     ` Jacob Pan
2020-07-01 15:33 ` [PATCH v3 7/7] iommu/vt-d: Disable multiple GPASID-dev bind Jacob Pan
2020-07-02  8:50   ` Auger Eric

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