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[86.59.218.44]) by smtp.gmail.com with ESMTPSA id y2sm14868321wmg.25.2020.08.22.14.03.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 22 Aug 2020 14:03:47 -0700 (PDT) From: "Saheed O. Bolarinwa" To: helgaas@kernel.org Date: Sat, 22 Aug 2020 22:03:46 +0200 Message-Id: <20200822200358.252967-12-refactormyself@gmail.com> X-Mailer: git-send-email 2.18.4 In-Reply-To: <20200822200358.252967-1-refactormyself@gmail.com> References: <20200822200358.252967-1-refactormyself@gmail.com> Cc: "Saheed O. Bolarinwa" , linux-kernel-mentees@lists.linuxfoundation.org Subject: [Linux-kernel-mentees] [RFC PATCH v5 11/23] PCI: Rework and Rename aspm_calc_l1ss_info() X-BeenThere: linux-kernel-mentees@lists.linuxfoundation.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Errors-To: linux-kernel-mentees-bounces@lists.linuxfoundation.org Sender: "Linux-kernel-mentees" The value of l1ss_cap_ptr can nw be obtained directly from struct pci_dev, it is no useful to cache it. So, aspm_calc_l1ss_info() will only be computing the values of ctl1 and ctl2. - Rename aspm_calc_l1ss_info() to aspm_calc_l1ss_ctl_values(). - Rework the function to take a pci_dev and values' pointer. - Remove caching of pdev->l1ss_cap_ptr - Change calls to aspm_calc_l1ss_info() into new function. - Access pdev->l1ss_cap_ptr directly - No more reference to struct pcie_link_state.l1ss, so remove it. Signed-off-by: Saheed O. Bolarinwa --- drivers/pci/pcie/aspm.c | 43 ++++++++++++++--------------------------- 1 file changed, 15 insertions(+), 28 deletions(-) diff --git a/drivers/pci/pcie/aspm.c b/drivers/pci/pcie/aspm.c index 89f3f3a6d007..4cff11dc8d83 100644 --- a/drivers/pci/pcie/aspm.c +++ b/drivers/pci/pcie/aspm.c @@ -74,14 +74,6 @@ struct pcie_link_state { * has one slot under it, so at most there are 8 functions. */ struct aspm_latency acceptable[8]; - - /* L1 PM Substate info */ - struct { - u32 up_cap_ptr; /* L1SS cap ptr in upstream dev */ - u32 dw_cap_ptr; /* L1SS cap ptr in downstream dev */ - u32 ctl1; /* value to be programmed in ctl1 */ - u32 ctl2; /* value to be programmed in ctl2 */ - } l1ss; }; static int aspm_disabled, aspm_force; @@ -444,17 +436,15 @@ static struct pci_dev *pci_function_0(struct pci_bus *linkbus) } /* Calculate L1.2 PM substate timing parameters */ -static void aspm_calc_l1ss_info(struct pcie_link_state *link) +static void aspm_calc_l1ss_ctl_values(struct pci_dev *pdev, + u32 *ctl1, u32 *ctl2) { + struct pcie_link_state *link = pdev->link_state; u32 val1, val2, scale1, scale2; u32 t_common_mode, t_power_on, l1_2_threshold, scale, value; struct pci_dev *dw_pdev = link->downstream; struct pci_dev *up_pdev = link->pdev; - link->l1ss.up_cap_ptr = up_pdev->l1ss_cap_ptr; - link->l1ss.dw_cap_ptr = dw_pdev->l1ss_cap_ptr; - link->l1ss.ctl1 = link->l1ss.ctl2 = 0; - if (!(link->aspm_support & ASPM_STATE_L1_2_MASK)) return; @@ -471,10 +461,10 @@ static void aspm_calc_l1ss_info(struct pcie_link_state *link) if (calc_l1ss_pwron(up_pdev, scale1, val1) > calc_l1ss_pwron(dw_pdev, scale2, val2)) { - link->l1ss.ctl2 |= scale1 | (val1 << 3); + *ctl2 |= scale1 | (val1 << 3); t_power_on = calc_l1ss_pwron(up_pdev, scale1, val1); } else { - link->l1ss.ctl2 |= scale2 | (val2 << 3); + *ctl2 |= scale2 | (val2 << 3); t_power_on = calc_l1ss_pwron(dw_pdev, scale2, val2); } @@ -490,7 +480,7 @@ static void aspm_calc_l1ss_info(struct pcie_link_state *link) */ l1_2_threshold = 2 + 4 + t_common_mode + t_power_on; encode_l12_threshold(l1_2_threshold, &scale, &value); - link->l1ss.ctl1 |= t_common_mode << 8 | scale << 29 | value << 16; + *ctl1 |= t_common_mode << 8 | scale << 29 | value << 16; } static u32 get_aspm_enable(struct pci_dev *pdev) @@ -620,13 +610,13 @@ static void pci_clear_and_set_dword(struct pci_dev *pdev, int pos, /* Configure the ASPM L1 substates */ static void pcie_config_aspm_l1ss(struct pcie_link_state *link, u32 state) { - u32 val, enable_req; + u32 val, enable_req, ctl1, ctl2; struct pci_dev *child = link->downstream, *parent = link->pdev; - u32 up_cap_ptr = link->l1ss.up_cap_ptr; - u32 dw_cap_ptr = link->l1ss.dw_cap_ptr; + int up_cap_ptr = parent->l1ss_cap_ptr; + int dw_cap_ptr = child->l1ss_cap_ptr; enable_req = (parent->aspm_enabled ^ state) & state; - aspm_calc_l1ss_info(link); + aspm_calc_l1ss_ctl_values(parent, &ctl1, &ctl2); /* * Here are the rules specified in the PCIe spec for enabling L1SS: @@ -661,24 +651,21 @@ static void pcie_config_aspm_l1ss(struct pcie_link_state *link, u32 state) /* Program T_POWER_ON times in both ports */ pci_write_config_dword(parent, up_cap_ptr + PCI_L1SS_CTL2, - link->l1ss.ctl2); + ctl2); pci_write_config_dword(child, dw_cap_ptr + PCI_L1SS_CTL2, - link->l1ss.ctl2); + ctl2); /* Program Common_Mode_Restore_Time in upstream device */ pci_clear_and_set_dword(parent, up_cap_ptr + PCI_L1SS_CTL1, - PCI_L1SS_CTL1_CM_RESTORE_TIME, - link->l1ss.ctl1); + PCI_L1SS_CTL1_CM_RESTORE_TIME, ctl1); /* Program LTR_L1.2_THRESHOLD time in both ports */ pci_clear_and_set_dword(parent, up_cap_ptr + PCI_L1SS_CTL1, PCI_L1SS_CTL1_LTR_L12_TH_VALUE | - PCI_L1SS_CTL1_LTR_L12_TH_SCALE, - link->l1ss.ctl1); + PCI_L1SS_CTL1_LTR_L12_TH_SCALE, ctl1); pci_clear_and_set_dword(child, dw_cap_ptr + PCI_L1SS_CTL1, PCI_L1SS_CTL1_LTR_L12_TH_VALUE | - PCI_L1SS_CTL1_LTR_L12_TH_SCALE, - link->l1ss.ctl1); + PCI_L1SS_CTL1_LTR_L12_TH_SCALE, ctl1); } val = 0; -- 2.18.4 _______________________________________________ Linux-kernel-mentees mailing list Linux-kernel-mentees@lists.linuxfoundation.org https://lists.linuxfoundation.org/mailman/listinfo/linux-kernel-mentees