From: Richard Zhu <hongxing.zhu@nxp.com>
To: l.stach@pengutronix.de, kishon@ti.com, vkoul@kernel.org,
robh@kernel.org, galak@kernel.crashing.org, shawnguo@kernel.org
Cc: linux-phy@lists.infradead.org, devicetree@vger.kernel.org,
linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org, kernel@pengutronix.de,
linux-imx@nxp.com, Richard Zhu <hongxing.zhu@nxp.com>
Subject: [PATCH 2/4] dt-bindings: phy: add imx8 pcie phy driver support
Date: Fri, 17 Sep 2021 10:31:01 +0800 [thread overview]
Message-ID: <1631845863-24249-3-git-send-email-hongxing.zhu@nxp.com> (raw)
In-Reply-To: <1631845863-24249-1-git-send-email-hongxing.zhu@nxp.com>
Add dt-binding for the standalone i.MX8 PCIe PHY driver.
Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
---
.../bindings/phy/fsl,imx8-pcie-phy.yaml | 66 +++++++++++++++++++
1 file changed, 66 insertions(+)
create mode 100644 Documentation/devicetree/bindings/phy/fsl,imx8-pcie-phy.yaml
diff --git a/Documentation/devicetree/bindings/phy/fsl,imx8-pcie-phy.yaml b/Documentation/devicetree/bindings/phy/fsl,imx8-pcie-phy.yaml
new file mode 100644
index 000000000000..2a81a17f1779
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/fsl,imx8-pcie-phy.yaml
@@ -0,0 +1,66 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/phy/fsl,imx8-pcie-phy.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Freescale i.MX8 SoC series PCIe PHY Device Tree Bindings
+
+maintainers:
+ - Richard Zhu <hongxing.zhu@nxp.com>
+
+properties:
+ "#phy-cells":
+ const: 0
+
+ compatible:
+ enum:
+ - fsl,imx8mm-pcie-phy
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ items:
+ - description: PHY module clock
+
+ clock-names:
+ items:
+ - const: phy
+
+ fsl,refclk-pad-mode:
+ description:
+ Specifies the mode of the refclk pad used. It can be NO_USED(PHY
+ refclock is derived from SoC internal source), INPUT(PHY refclock
+ is provided externally via the refclk pad) or OUTPUT(PHY refclock
+ is derived from SoC internal source and provided on the refclk pad).
+ Refer include/dt-bindings/phy/phy-imx8-pcie.h for the constants
+ to be used.
+ enum: [ 0, 1, 2 ]
+
+required:
+ - "#phy-cells"
+ - compatible
+ - reg
+ - clocks
+ - clock-names
+ - fsl,refclk-pad-mode
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/imx8mm-clock.h>
+
+ pcie_phy: pcie-phy@32f00000 {
+ compatible = "fsl,imx8mm-pcie-phy";
+ reg = <0x32f00000 0x10000>;
+ clocks = <&clk IMX8MM_CLK_PCIE1_PHY>;
+ clock-names = "phy";
+ assigned-clocks = <&clk IMX8MM_CLK_PCIE1_PHY>;
+ assigned-clock-rates = <100000000>;
+ assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_100M>;
+ fsl,refclk-pad-mode = <1>;
+ #phy-cells = <0>;
+ };
+...
--
2.25.1
next prev parent reply other threads:[~2021-09-17 2:54 UTC|newest]
Thread overview: 11+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-09-17 2:30 [PATCH 0/4] add the imx8 pcie phy driver support Richard Zhu
2021-09-17 2:31 ` [PATCH 1/4] dt-bindings: phy: phy-imx8-pcie: Add binding for the pad modes of imx8 pcie phy Richard Zhu
2021-09-22 19:25 ` Rob Herring
2021-09-23 5:56 ` Richard Zhu
2021-09-23 14:43 ` Rob Herring
2021-09-24 2:08 ` Richard Zhu
2021-09-17 2:31 ` Richard Zhu [this message]
2021-09-17 19:48 ` [PATCH 2/4] dt-bindings: phy: add imx8 pcie phy driver support Rob Herring
2021-09-22 8:24 ` Richard Zhu
2021-09-17 2:31 ` [PATCH 3/4] arm64: dts: imx8mm: add the pcie phy support Richard Zhu
2021-09-17 2:31 ` [PATCH 4/4] phy: freescale: pcie: initialize the imx8 pcie standalone phy driver Richard Zhu
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