From: Kishon Vijay Abraham I <kishon@ti.com>
To: Kishon Vijay Abraham I <kishon@ti.com>,
Vinod Koul <vkoul@kernel.org>, Rob Herring <robh+dt@kernel.org>,
Nishanth Menon <nm@ti.com>,
Philipp Zabel <p.zabel@pengutronix.de>
Cc: <linux-kernel@vger.kernel.org>, <devicetree@vger.kernel.org>,
<linux-arm-kernel@lists.infradead.org>
Subject: [PATCH v3 00/15] PHY: Add support in Sierra to use external clock
Date: Thu, 24 Dec 2020 16:46:12 +0530 [thread overview]
Message-ID: <20201224111627.32590-1-kishon@ti.com> (raw)
Patch series adds support in Sierra driver to use external clock.
v1 of the patch series can be found @ [1]
v2 of the patch series can be found @ [2]
Changes from v2:
1) Add depends on COMMON_CLK in Sierra
2) Add modelling PLL_CMNLC and PLL_CMNLC1 as clocks into a separate
patch
3) Disable clocks in Sierra driver remove
Changes from v1:
1) Remove the part that prevents configuration if the SERDES is already
configured and focus only on using external clock and the associated
cleanups
2) Change patch ordering
3) Use exclusive reset control APIs
4) Fix error handling code
5) Include DT patches in this series (I can send this separately to DT
MAINTAINER once the driver patches are merged)
[1] -> http://lore.kernel.org/r/20201103035556.21260-1-kishon@ti.com
[2] -> http://lore.kernel.org/r/20201222070520.28132-1-kishon@ti.com
Kishon Vijay Abraham I (15):
phy: cadence: Sierra: Fix PHY power_on sequence
phy: ti: j721e-wiz: Invoke wiz_init() before
of_platform_device_create()
dt-bindings: phy: cadence-sierra: Add bindings for the PLLs within
SERDES
phy: ti: j721e-wiz: Get PHY properties only for "phy" or "link"
subnode
phy: cadence: cadence-sierra: Create PHY only for "phy" or "link"
sub-nodes
phy: cadence: cadence-sierra: Move all clk_get_*() to a separate
function
phy: cadence: cadence-sierra: Move all reset_control_get*() to a
separate function
phy: cadence: cadence-sierra: Explicitly request exclusive reset
control
phy: cadence: sierra: Model reference receiver as clocks (gate clocks)
phy: cadence: sierra: Model PLL_CMNLC and PLL_CMNLC1 as clocks (mux
clocks)
phy: cadence: sierra: Enable pll_cmnlc and pll_cmnlc1 clocks
arm64: dts: ti: k3-j721e-main: Add DT nodes for clocks within Sierra
SERDES
arm64: dts: ti: k3-j721e-main: Fix external refclk input to SERDES
arm64: dts: ti: k3-j721e-common-proc-board: Use external clock for
SERDES
arm64: dts: ti: k3-j721e-common-proc-board: Re-name "link" name as
"phy"
.../bindings/phy/phy-cadence-sierra.yaml | 89 ++-
.../dts/ti/k3-j721e-common-proc-board.dts | 57 +-
arch/arm64/boot/dts/ti/k3-j721e-main.dtsi | 186 ++++--
drivers/phy/cadence/Kconfig | 1 +
drivers/phy/cadence/phy-cadence-sierra.c | 544 ++++++++++++++++--
drivers/phy/ti/phy-j721e-wiz.c | 21 +-
6 files changed, 810 insertions(+), 88 deletions(-)
--
2.17.1
next reply other threads:[~2020-12-24 11:18 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-12-24 11:16 Kishon Vijay Abraham I [this message]
2020-12-24 11:16 ` [PATCH v3 01/15] phy: cadence: Sierra: Fix PHY power_on sequence Kishon Vijay Abraham I
2020-12-24 11:16 ` [PATCH v3 02/15] phy: ti: j721e-wiz: Invoke wiz_init() before of_platform_device_create() Kishon Vijay Abraham I
2020-12-24 11:16 ` [PATCH v3 03/15] dt-bindings: phy: cadence-sierra: Add bindings for the PLLs within SERDES Kishon Vijay Abraham I
2020-12-24 11:16 ` [PATCH v3 04/15] phy: ti: j721e-wiz: Get PHY properties only for "phy" or "link" subnode Kishon Vijay Abraham I
2020-12-24 11:16 ` [PATCH v3 05/15] phy: cadence: cadence-sierra: Create PHY only for "phy" or "link" sub-nodes Kishon Vijay Abraham I
2020-12-24 11:16 ` [PATCH v3 06/15] phy: cadence: cadence-sierra: Move all clk_get_*() to a separate function Kishon Vijay Abraham I
2020-12-24 11:16 ` [PATCH v3 07/15] phy: cadence: cadence-sierra: Move all reset_control_get*() " Kishon Vijay Abraham I
2020-12-24 11:16 ` [PATCH v3 08/15] phy: cadence: cadence-sierra: Explicitly request exclusive reset control Kishon Vijay Abraham I
2020-12-24 11:16 ` [PATCH v3 09/15] phy: cadence: sierra: Model reference receiver as clocks (gate clocks) Kishon Vijay Abraham I
2020-12-24 11:16 ` [PATCH v3 10/15] phy: cadence: sierra: Model PLL_CMNLC and PLL_CMNLC1 as clocks (mux clocks) Kishon Vijay Abraham I
2020-12-24 11:16 ` [PATCH v3 11/15] phy: cadence: sierra: Enable pll_cmnlc and pll_cmnlc1 clocks Kishon Vijay Abraham I
2020-12-24 11:16 ` [PATCH v3 12/15] arm64: dts: ti: k3-j721e-main: Add DT nodes for clocks within Sierra SERDES Kishon Vijay Abraham I
2020-12-24 11:16 ` [PATCH v3 13/15] arm64: dts: ti: k3-j721e-main: Fix external refclk input to SERDES Kishon Vijay Abraham I
2020-12-24 11:16 ` [PATCH v3 14/15] arm64: dts: ti: k3-j721e-common-proc-board: Use external clock for SERDES Kishon Vijay Abraham I
2020-12-24 11:16 ` [PATCH v3 15/15] arm64: dts: ti: k3-j721e-common-proc-board: Re-name "link" name as "phy" Kishon Vijay Abraham I
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