From: Ryan Chen <ryan_chen@aspeedtech.com>
To: Michael Turquette <mturquette@baylibre.com>,
Stephen Boyd <sboyd@kernel.org>, <linux-clk@vger.kernel.org>,
<linux-kernel@vger.kernel.org>, <andrewrj@aj.id.au>,
<joel@linux.ibm.com>, <BMC-SW@aspeedtech.com>
Cc: Ryan Chen <ryan_chen@aspeedtech.com>
Subject: [PATCH v2] clk: aspeed: Fix APLL calculate formula from ast2600-A2
Date: Tue, 19 Jan 2021 14:17:15 +0800 [thread overview]
Message-ID: <20210119061715.6043-1-ryan_chen@aspeedtech.com> (raw)
In-Reply-To: <20210118100813.30821-2-ryan_chen@aspeedtech.com>
Starting from A2, the A-PLL calculation has changed. Use the
existing formula for A0/A1 and the new formula for A2 onwards.
Fixes: d3d04f6c330a ("clk: Add support for AST2600 SoC")
Signed-off-by: Ryan Chen <ryan_chen@aspeedtech.com>
---
drivers/clk/clk-ast2600.c | 37 +++++++++++++++++++++++++++----------
1 file changed, 27 insertions(+), 10 deletions(-)
diff --git a/drivers/clk/clk-ast2600.c b/drivers/clk/clk-ast2600.c
index bbacaccad554..8933bd1506b3 100644
--- a/drivers/clk/clk-ast2600.c
+++ b/drivers/clk/clk-ast2600.c
@@ -17,7 +17,8 @@
#define ASPEED_G6_NUM_CLKS 71
-#define ASPEED_G6_SILICON_REV 0x004
+#define ASPEED_G6_SILICON_REV 0x014
+#define CHIP_REVISION_ID GENMASK(23, 16)
#define ASPEED_G6_RESET_CTRL 0x040
#define ASPEED_G6_RESET_CTRL2 0x050
@@ -190,18 +191,34 @@ static struct clk_hw *ast2600_calc_pll(const char *name, u32 val)
static struct clk_hw *ast2600_calc_apll(const char *name, u32 val)
{
unsigned int mult, div;
+ u32 chip_id = readl(scu_g6_base + ASPEED_G6_SILICON_REV);
- if (val & BIT(20)) {
- /* Pass through mode */
- mult = div = 1;
+ if (((chip_id & CHIP_REVISION_ID) >> 16) >= 2) {
+ if (val & BIT(24)) {
+ /* Pass through mode */
+ mult = div = 1;
+ } else {
+ /* F = 25Mhz * [(m + 1) / (n + 1)] / (p + 1) */
+ u32 m = val & 0x1fff;
+ u32 n = (val >> 13) & 0x3f;
+ u32 p = (val >> 19) & 0xf;
+
+ mult = (m + 1);
+ div = (n + 1) * (p + 1);
+ }
} else {
- /* F = 25Mhz * (2-od) * [(m + 2) / (n + 1)] */
- u32 m = (val >> 5) & 0x3f;
- u32 od = (val >> 4) & 0x1;
- u32 n = val & 0xf;
+ if (val & BIT(20)) {
+ /* Pass through mode */
+ mult = div = 1;
+ } else {
+ /* F = 25Mhz * (2-od) * [(m + 2) / (n + 1)] */
+ u32 m = (val >> 5) & 0x3f;
+ u32 od = (val >> 4) & 0x1;
+ u32 n = val & 0xf;
- mult = (2 - od) * (m + 2);
- div = n + 1;
+ mult = (2 - od) * (m + 2);
+ div = n + 1;
+ }
}
return clk_hw_register_fixed_factor(NULL, name, "clkin", 0,
mult, div);
--
2.17.1
next prev parent reply other threads:[~2021-01-19 6:29 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-01-18 10:08 [PATCH 0/1] Fix AST2600A2 APLL calculate formuula Ryan Chen
2021-01-18 10:08 ` [PATCH 1/1] clk: aspeed: Fix APLL calculate formula for ast2600-A2 Ryan Chen
2021-01-19 2:20 ` Joel Stanley
2021-01-19 3:04 ` Ryan Chen
2021-01-19 3:10 ` Joel Stanley
2021-01-19 3:29 ` Ryan Chen
2021-01-19 6:17 ` Ryan Chen [this message]
2021-01-19 11:48 ` [PATCH v2] clk: aspeed: Fix APLL calculate formula from ast2600-A2 Joel Stanley
2021-02-11 20:36 ` Stephen Boyd
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