From: Stephane Eranian <eranian@google.com>
To: linux-kernel@vger.kernel.org
Cc: peterz@infradead.org, acme@redhat.com, jolsa@redhat.com,
kim.phillips@amd.com, namhyung@kernel.org, irogers@google.com
Subject: [PATCH v1 01/13] perf/core: add union to struct perf_branch_entry
Date: Thu, 9 Sep 2021 00:56:48 -0700 [thread overview]
Message-ID: <20210909075700.4025355-2-eranian@google.com> (raw)
In-Reply-To: <20210909075700.4025355-1-eranian@google.com>
To make it simpler to reset all the info fields on the perf_branch_entry in
a single store, we use a union. This avoids missing some of the bitfields and
improves generated code by minimizing the number of stores.
Using an anonymous struct around the bitfields to guarantee field ordering.
A single perf_branch_entry.val = 0 guarantees all fields are all zeroes on any arch.
Signed-off-by: Stephane Eranian <eranian@google.com>
---
arch/x86/events/intel/lbr.c | 13 +++----------
include/uapi/linux/perf_event.h | 19 ++++++++++++-------
2 files changed, 15 insertions(+), 17 deletions(-)
diff --git a/arch/x86/events/intel/lbr.c b/arch/x86/events/intel/lbr.c
index 9e6d6eaeb4cb..27aa48cce3c6 100644
--- a/arch/x86/events/intel/lbr.c
+++ b/arch/x86/events/intel/lbr.c
@@ -801,15 +801,9 @@ void intel_pmu_lbr_read_32(struct cpu_hw_events *cpuc)
rdmsrl(x86_pmu.lbr_from + lbr_idx, msr_lastbranch.lbr);
+ cpuc->lbr_entries[i].val = 0;
cpuc->lbr_entries[i].from = msr_lastbranch.from;
cpuc->lbr_entries[i].to = msr_lastbranch.to;
- cpuc->lbr_entries[i].mispred = 0;
- cpuc->lbr_entries[i].predicted = 0;
- cpuc->lbr_entries[i].in_tx = 0;
- cpuc->lbr_entries[i].abort = 0;
- cpuc->lbr_entries[i].cycles = 0;
- cpuc->lbr_entries[i].type = 0;
- cpuc->lbr_entries[i].reserved = 0;
}
cpuc->lbr_stack.nr = i;
cpuc->lbr_stack.hw_idx = tos;
@@ -896,6 +890,7 @@ void intel_pmu_lbr_read_64(struct cpu_hw_events *cpuc)
if (abort && x86_pmu.lbr_double_abort && out > 0)
out--;
+ cpuc->lbr_entries[out].val = 0;
cpuc->lbr_entries[out].from = from;
cpuc->lbr_entries[out].to = to;
cpuc->lbr_entries[out].mispred = mis;
@@ -903,8 +898,6 @@ void intel_pmu_lbr_read_64(struct cpu_hw_events *cpuc)
cpuc->lbr_entries[out].in_tx = in_tx;
cpuc->lbr_entries[out].abort = abort;
cpuc->lbr_entries[out].cycles = cycles;
- cpuc->lbr_entries[out].type = 0;
- cpuc->lbr_entries[out].reserved = 0;
out++;
}
cpuc->lbr_stack.nr = out;
@@ -966,6 +959,7 @@ static void intel_pmu_store_lbr(struct cpu_hw_events *cpuc,
to = rdlbr_to(i, lbr);
info = rdlbr_info(i, lbr);
+ e->val = 0;
e->from = from;
e->to = to;
e->mispred = get_lbr_mispred(info);
@@ -974,7 +968,6 @@ static void intel_pmu_store_lbr(struct cpu_hw_events *cpuc,
e->abort = !!(info & LBR_INFO_ABORT);
e->cycles = get_lbr_cycles(info);
e->type = get_lbr_br_type(info);
- e->reserved = 0;
}
cpuc->lbr_stack.nr = i;
diff --git a/include/uapi/linux/perf_event.h b/include/uapi/linux/perf_event.h
index f92880a15645..eb11f383f4be 100644
--- a/include/uapi/linux/perf_event.h
+++ b/include/uapi/linux/perf_event.h
@@ -1329,13 +1329,18 @@ union perf_mem_data_src {
struct perf_branch_entry {
__u64 from;
__u64 to;
- __u64 mispred:1, /* target mispredicted */
- predicted:1,/* target predicted */
- in_tx:1, /* in transaction */
- abort:1, /* transaction abort */
- cycles:16, /* cycle count to last branch */
- type:4, /* branch type */
- reserved:40;
+ union {
+ __u64 val; /* to make it easier to clear all fields */
+ struct {
+ __u64 mispred:1, /* target mispredicted */
+ predicted:1,/* target predicted */
+ in_tx:1, /* in transaction */
+ abort:1, /* transaction abort */
+ cycles:16, /* cycle count to last branch */
+ type:4, /* branch type */
+ reserved:40;
+ };
+ };
};
union perf_sample_weight {
--
2.33.0.153.gba50c8fa24-goog
next prev parent reply other threads:[~2021-09-09 7:58 UTC|newest]
Thread overview: 41+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-09-09 7:56 [PATCH v1 00/13] perf/x86/amd: Add AMD Fam19h Branch Sampling support Stephane Eranian
2021-09-09 7:56 ` Stephane Eranian [this message]
2021-09-09 19:03 ` [PATCH v1 01/13] perf/core: add union to struct perf_branch_entry Peter Zijlstra
2021-09-10 12:09 ` Michael Ellerman
2021-09-10 14:16 ` Michael Ellerman
2021-09-15 6:03 ` Stephane Eranian
2021-09-17 6:37 ` Madhavan Srinivasan
2021-09-17 6:48 ` Stephane Eranian
2021-09-17 7:05 ` Michael Ellerman
2021-09-17 7:39 ` Stephane Eranian
2021-09-17 12:38 ` Michael Ellerman
2021-09-17 16:42 ` Stephane Eranian
2021-09-19 10:27 ` Michael Ellerman
2021-09-09 7:56 ` [PATCH v1 02/13] x86/cpufeatures: add AMD Fam19h Branch Sampling feature Stephane Eranian
2021-09-09 7:56 ` [PATCH v1 03/13] perf/x86/amd: add AMD Fam19h Branch Sampling support Stephane Eranian
2021-09-09 10:44 ` kernel test robot
2021-09-09 15:33 ` kernel test robot
2021-09-09 7:56 ` [PATCH v1 04/13] perf/x86/amd: add branch-brs helper event for Fam19h BRS Stephane Eranian
2021-09-09 7:56 ` [PATCH v1 05/13] perf/x86/amd: enable branch sampling priv level filtering Stephane Eranian
2021-09-09 7:56 ` [PATCH v1 06/13] perf/x86/amd: add AMD branch sampling period adjustment Stephane Eranian
2021-09-09 7:56 ` [PATCH v1 07/13] perf/core: add idle hooks Stephane Eranian
2021-09-09 9:15 ` Peter Zijlstra
2021-09-09 10:42 ` kernel test robot
2021-09-09 11:02 ` kernel test robot
2021-09-09 7:56 ` [PATCH v1 08/13] perf/x86/core: " Stephane Eranian
2021-09-09 9:16 ` Peter Zijlstra
2021-09-09 7:56 ` [PATCH v1 09/13] perf/x86/amd: add idle hooks for branch sampling Stephane Eranian
2021-09-09 9:20 ` Peter Zijlstra
2021-09-09 7:56 ` [PATCH v1 10/13] perf tools: add branch-brs as a new event Stephane Eranian
2021-09-09 7:56 ` [PATCH v1 11/13] perf tools: improve IBS error handling Stephane Eranian
2021-09-13 19:34 ` Arnaldo Carvalho de Melo
2021-10-04 21:57 ` Kim Phillips
2021-10-04 23:44 ` Arnaldo Carvalho de Melo
2021-09-09 7:56 ` [PATCH v1 12/13] perf tools: improve error handling of AMD Branch Sampling Stephane Eranian
2021-10-04 21:57 ` Kim Phillips
2021-09-09 7:57 ` [PATCH v1 13/13] perf report: add addr_from/addr_to sort dimensions Stephane Eranian
2021-09-09 8:55 ` [PATCH v1 00/13] perf/x86/amd: Add AMD Fam19h Branch Sampling support Peter Zijlstra
2021-09-15 5:55 ` Stephane Eranian
2021-09-15 9:04 ` Peter Zijlstra
2021-10-28 18:30 ` Stephane Eranian
2021-09-27 20:17 ` Song Liu
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20210909075700.4025355-2-eranian@google.com \
--to=eranian@google.com \
--cc=acme@redhat.com \
--cc=irogers@google.com \
--cc=jolsa@redhat.com \
--cc=kim.phillips@amd.com \
--cc=linux-kernel@vger.kernel.org \
--cc=namhyung@kernel.org \
--cc=peterz@infradead.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).