[PATCH 1/5] m68knommu: fix overwriting of bits in ColdFire V3 cache control

[PATCH 1/5] m68knommu: fix overwriting of bits in ColdFire V3 cache control

[Greg Ungerer]

The Cache Control Register (CACR) of the ColdFire V3 has bits that
control high level caching functions, and also enable/disable the use
of the alternate stack pointer register (the EUSP bit) to provide
separate supervisor and user stack pointer registers. The code as
it is today will blindly clear the EUSP bit on cache actions like
invalidation. So it is broken for this case - and that will result
in failed booting (interrupt entry and exit processing will be
completely hosed).

This only affects ColdFire V3 parts that support the alternate stack
register (like the 5329 for example) - generally speaking new parts do,
older parts don't. It has no impact on ColdFire V3 parts with the single
stack pointer, like the 5307 for example.

Fix the cache bit defines used, so they maintain the EUSP bit when
carrying out cache actions through the CACR register.

Signed-off-by: Greg Ungerer <gerg@linux-m68k.org>
---
 arch/m68k/include/asm/m53xxacr.h | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/arch/m68k/include/asm/m53xxacr.h b/arch/m68k/include/asm/m53xxacr.h
index 9138a624c5c8..25b144495234 100644
--- a/arch/m68k/include/asm/m53xxacr.h
+++ b/arch/m68k/include/asm/m53xxacr.h
@@ -89,9 +89,9 @@
  * coherency though in all cases. And for copyback caches we will need
  * to push cached data as well.
  */
-#define CACHE_INIT	  CACR_CINVA
-#define CACHE_INVALIDATE  CACR_CINVA
-#define CACHE_INVALIDATED CACR_CINVA
+#define CACHE_INIT        (CACHE_MODE + CACR_CINVA)
+#define CACHE_INVALIDATE  (CACHE_MODE + CACR_CINVA)
+#define CACHE_INVALIDATED (CACHE_MODE + CACR_CINVA)
 
 #define ACR0_MODE	((CONFIG_RAMBASE & 0xff000000) + \
 			 (0x000f0000) + \
-- 
2.25.1

Re: [PATCH 1/5] m68knommu: fix overwriting of bits in ColdFire V3 cache control

[Geert Uytterhoeven]

Hi Greg,

On Mon, Jun 15, 2020 at 8:38 AM Greg Ungerer <gerg@linux-m68k.org> wrote:
> The Cache Control Register (CACR) of the ColdFire V3 has bits that
> control high level caching functions, and also enable/disable the use
> of the alternate stack pointer register (the EUSP bit) to provide
> separate supervisor and user stack pointer registers. The code as
> it is today will blindly clear the EUSP bit on cache actions like
> invalidation. So it is broken for this case - and that will result
> in failed booting (interrupt entry and exit processing will be
> completely hosed).
>
> This only affects ColdFire V3 parts that support the alternate stack
> register (like the 5329 for example) - generally speaking new parts do,
> older parts don't. It has no impact on ColdFire V3 parts with the single
> stack pointer, like the 5307 for example.
>
> Fix the cache bit defines used, so they maintain the EUSP bit when
> carrying out cache actions through the CACR register.
>
> Signed-off-by: Greg Ungerer <gerg@linux-m68k.org>

Thanks for your patch!

> --- a/arch/m68k/include/asm/m53xxacr.h
> +++ b/arch/m68k/include/asm/m53xxacr.h
> @@ -89,9 +89,9 @@
>   * coherency though in all cases. And for copyback caches we will need
>   * to push cached data as well.
>   */
> -#define CACHE_INIT       CACR_CINVA
> -#define CACHE_INVALIDATE  CACR_CINVA
> -#define CACHE_INVALIDATED CACR_CINVA
> +#define CACHE_INIT        (CACHE_MODE + CACR_CINVA)

This line is different from the RFC v2 in
https://www.spinics.net/lists/linux-m68k/msg13973.html ?

> +#define CACHE_INVALIDATE  (CACHE_MODE + CACR_CINVA)
> +#define CACHE_INVALIDATED (CACHE_MODE + CACR_CINVA)

Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

Re: [PATCH 1/5] m68knommu: fix overwriting of bits in ColdFire V3 cache control

[Greg Ungerer]

Hi Geert,

On 15/6/20 9:26 pm, Geert Uytterhoeven wrote:
> On Mon, Jun 15, 2020 at 8:38 AM Greg Ungerer <gerg@linux-m68k.org> wrote:
>> The Cache Control Register (CACR) of the ColdFire V3 has bits that
>> control high level caching functions, and also enable/disable the use
>> of the alternate stack pointer register (the EUSP bit) to provide
>> separate supervisor and user stack pointer registers. The code as
>> it is today will blindly clear the EUSP bit on cache actions like
>> invalidation. So it is broken for this case - and that will result
>> in failed booting (interrupt entry and exit processing will be
>> completely hosed).
>>
>> This only affects ColdFire V3 parts that support the alternate stack
>> register (like the 5329 for example) - generally speaking new parts do,
>> older parts don't. It has no impact on ColdFire V3 parts with the single
>> stack pointer, like the 5307 for example.
>>
>> Fix the cache bit defines used, so they maintain the EUSP bit when
>> carrying out cache actions through the CACR register.
>>
>> Signed-off-by: Greg Ungerer <gerg@linux-m68k.org>
> 
> Thanks for your patch!
> 
>> --- a/arch/m68k/include/asm/m53xxacr.h
>> +++ b/arch/m68k/include/asm/m53xxacr.h
>> @@ -89,9 +89,9 @@
>>    * coherency though in all cases. And for copyback caches we will need
>>    * to push cached data as well.
>>    */
>> -#define CACHE_INIT       CACR_CINVA
>> -#define CACHE_INVALIDATE  CACR_CINVA
>> -#define CACHE_INVALIDATED CACR_CINVA
>> +#define CACHE_INIT        (CACHE_MODE + CACR_CINVA)
> 
> This line is different from the RFC v2 in
> https://www.spinics.net/lists/linux-m68k/msg13973.html ?

Thanks Geert, you are absolutely correct. I will generate a v2
with the correct change.

Regards
Greg