Linux-m68k Archive on lore.kernel.org
 help / color / Atom feed
* [PATCH 1/5] m68knommu: fix overwriting of bits in ColdFire V3 cache control
@ 2020-06-15  6:35 Greg Ungerer
  2020-06-15 11:26 ` Geert Uytterhoeven
  0 siblings, 1 reply; 3+ messages in thread
From: Greg Ungerer @ 2020-06-15  6:35 UTC (permalink / raw)
  To: linux-m68k; +Cc: Greg Ungerer

The Cache Control Register (CACR) of the ColdFire V3 has bits that
control high level caching functions, and also enable/disable the use
of the alternate stack pointer register (the EUSP bit) to provide
separate supervisor and user stack pointer registers. The code as
it is today will blindly clear the EUSP bit on cache actions like
invalidation. So it is broken for this case - and that will result
in failed booting (interrupt entry and exit processing will be
completely hosed).

This only affects ColdFire V3 parts that support the alternate stack
register (like the 5329 for example) - generally speaking new parts do,
older parts don't. It has no impact on ColdFire V3 parts with the single
stack pointer, like the 5307 for example.

Fix the cache bit defines used, so they maintain the EUSP bit when
carrying out cache actions through the CACR register.

Signed-off-by: Greg Ungerer <gerg@linux-m68k.org>
---
 arch/m68k/include/asm/m53xxacr.h | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/arch/m68k/include/asm/m53xxacr.h b/arch/m68k/include/asm/m53xxacr.h
index 9138a624c5c8..25b144495234 100644
--- a/arch/m68k/include/asm/m53xxacr.h
+++ b/arch/m68k/include/asm/m53xxacr.h
@@ -89,9 +89,9 @@
  * coherency though in all cases. And for copyback caches we will need
  * to push cached data as well.
  */
-#define CACHE_INIT	  CACR_CINVA
-#define CACHE_INVALIDATE  CACR_CINVA
-#define CACHE_INVALIDATED CACR_CINVA
+#define CACHE_INIT        (CACHE_MODE + CACR_CINVA)
+#define CACHE_INVALIDATE  (CACHE_MODE + CACR_CINVA)
+#define CACHE_INVALIDATED (CACHE_MODE + CACR_CINVA)
 
 #define ACR0_MODE	((CONFIG_RAMBASE & 0xff000000) + \
 			 (0x000f0000) + \
-- 
2.25.1


^ permalink raw reply	[flat|nested] 3+ messages in thread

* Re: [PATCH 1/5] m68knommu: fix overwriting of bits in ColdFire V3 cache control
  2020-06-15  6:35 [PATCH 1/5] m68knommu: fix overwriting of bits in ColdFire V3 cache control Greg Ungerer
@ 2020-06-15 11:26 ` Geert Uytterhoeven
  2020-06-15 13:32   ` Greg Ungerer
  0 siblings, 1 reply; 3+ messages in thread
From: Geert Uytterhoeven @ 2020-06-15 11:26 UTC (permalink / raw)
  To: Greg Ungerer; +Cc: Linux/m68k, Joachim Dietrich

Hi Greg,

On Mon, Jun 15, 2020 at 8:38 AM Greg Ungerer <gerg@linux-m68k.org> wrote:
> The Cache Control Register (CACR) of the ColdFire V3 has bits that
> control high level caching functions, and also enable/disable the use
> of the alternate stack pointer register (the EUSP bit) to provide
> separate supervisor and user stack pointer registers. The code as
> it is today will blindly clear the EUSP bit on cache actions like
> invalidation. So it is broken for this case - and that will result
> in failed booting (interrupt entry and exit processing will be
> completely hosed).
>
> This only affects ColdFire V3 parts that support the alternate stack
> register (like the 5329 for example) - generally speaking new parts do,
> older parts don't. It has no impact on ColdFire V3 parts with the single
> stack pointer, like the 5307 for example.
>
> Fix the cache bit defines used, so they maintain the EUSP bit when
> carrying out cache actions through the CACR register.
>
> Signed-off-by: Greg Ungerer <gerg@linux-m68k.org>

Thanks for your patch!

> --- a/arch/m68k/include/asm/m53xxacr.h
> +++ b/arch/m68k/include/asm/m53xxacr.h
> @@ -89,9 +89,9 @@
>   * coherency though in all cases. And for copyback caches we will need
>   * to push cached data as well.
>   */
> -#define CACHE_INIT       CACR_CINVA
> -#define CACHE_INVALIDATE  CACR_CINVA
> -#define CACHE_INVALIDATED CACR_CINVA
> +#define CACHE_INIT        (CACHE_MODE + CACR_CINVA)

This line is different from the RFC v2 in
https://www.spinics.net/lists/linux-m68k/msg13973.html ?

> +#define CACHE_INVALIDATE  (CACHE_MODE + CACR_CINVA)
> +#define CACHE_INVALIDATED (CACHE_MODE + CACR_CINVA)

Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

^ permalink raw reply	[flat|nested] 3+ messages in thread

* Re: [PATCH 1/5] m68knommu: fix overwriting of bits in ColdFire V3 cache control
  2020-06-15 11:26 ` Geert Uytterhoeven
@ 2020-06-15 13:32   ` Greg Ungerer
  0 siblings, 0 replies; 3+ messages in thread
From: Greg Ungerer @ 2020-06-15 13:32 UTC (permalink / raw)
  To: Geert Uytterhoeven; +Cc: Linux/m68k, Joachim Dietrich

Hi Geert,

On 15/6/20 9:26 pm, Geert Uytterhoeven wrote:
> On Mon, Jun 15, 2020 at 8:38 AM Greg Ungerer <gerg@linux-m68k.org> wrote:
>> The Cache Control Register (CACR) of the ColdFire V3 has bits that
>> control high level caching functions, and also enable/disable the use
>> of the alternate stack pointer register (the EUSP bit) to provide
>> separate supervisor and user stack pointer registers. The code as
>> it is today will blindly clear the EUSP bit on cache actions like
>> invalidation. So it is broken for this case - and that will result
>> in failed booting (interrupt entry and exit processing will be
>> completely hosed).
>>
>> This only affects ColdFire V3 parts that support the alternate stack
>> register (like the 5329 for example) - generally speaking new parts do,
>> older parts don't. It has no impact on ColdFire V3 parts with the single
>> stack pointer, like the 5307 for example.
>>
>> Fix the cache bit defines used, so they maintain the EUSP bit when
>> carrying out cache actions through the CACR register.
>>
>> Signed-off-by: Greg Ungerer <gerg@linux-m68k.org>
> 
> Thanks for your patch!
> 
>> --- a/arch/m68k/include/asm/m53xxacr.h
>> +++ b/arch/m68k/include/asm/m53xxacr.h
>> @@ -89,9 +89,9 @@
>>    * coherency though in all cases. And for copyback caches we will need
>>    * to push cached data as well.
>>    */
>> -#define CACHE_INIT       CACR_CINVA
>> -#define CACHE_INVALIDATE  CACR_CINVA
>> -#define CACHE_INVALIDATED CACR_CINVA
>> +#define CACHE_INIT        (CACHE_MODE + CACR_CINVA)
> 
> This line is different from the RFC v2 in
> https://www.spinics.net/lists/linux-m68k/msg13973.html ?

Thanks Geert, you are absolutely correct. I will generate a v2
with the correct change.

Regards
Greg


^ permalink raw reply	[flat|nested] 3+ messages in thread

end of thread, back to index

Thread overview: 3+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2020-06-15  6:35 [PATCH 1/5] m68knommu: fix overwriting of bits in ColdFire V3 cache control Greg Ungerer
2020-06-15 11:26 ` Geert Uytterhoeven
2020-06-15 13:32   ` Greg Ungerer

Linux-m68k Archive on lore.kernel.org

Archives are clonable:
	git clone --mirror https://lore.kernel.org/linux-m68k/0 linux-m68k/git/0.git

	# If you have public-inbox 1.1+ installed, you may
	# initialize and index your mirror using the following commands:
	public-inbox-init -V2 linux-m68k linux-m68k/ https://lore.kernel.org/linux-m68k \
		linux-m68k@vger.kernel.org linux-m68k@lists.linux-m68k.org
	public-inbox-index linux-m68k

Example config snippet for mirrors

Newsgroup available over NNTP:
	nntp://nntp.lore.kernel.org/org.kernel.vger.linux-m68k


AGPL code for this site: git clone https://public-inbox.org/public-inbox.git