Re: [PATCH] getauxval.3: Add new cache geometry entries

From: "G. Branden Robinson" <g.branden.robinson@gmail.com>
To: "Michael Kerrisk (man-pages)" <mtk.manpages@gmail.com>,
	linux-man@vger.kernel.org, benh@kernel.crashing.org,
	mpe@ellerman.id.au
Subject: Re: [PATCH] getauxval.3: Add new cache geometry entries
Date: Wed, 25 Sep 2019 04:41:59 +1000	[thread overview]
Message-ID: <20190924184158.3f3au7aqnitasrrn@localhost.localdomain> (raw)
In-Reply-To: <91faffae-777b-7e77-2986-463dc01508be@linux.vnet.ibm.com>

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At 2019-09-23T10:36:16-0300, Raphael M Zinsly wrote:
> > > +Geometry of the L1 data cache, that is, line size and number
> > > +of ways.
> > 
> > What is "number of ways"?
> 
> It is the cache associativity, e.g.: 8 means the cache is 8-way set
> associative.

Yup.  At some point when I wasn't looking, the "-way" in "n-way cache"
got promoted from a partial adjective along the lines of "all cars must
halt at the four-way stop sign" to a full-blooded noun and term of art.
I bumped into it while proofreading a Ph.D. thesis[1].

To help familiarize practitioners with the new cloak of terminology
draped over this hoary descendant of Old English "weg", I suggest adding
a parenthetical:

  Geometry of the L1 data cache; that is, line size and number of ways
  (e.g., \(lq4-way associative\(rq).

Regards,
Branden

[1] Ge, Qian, "Mitigating Microarchitecture-based Timing Channels with
Lightweight Operating System Mechanisms", Ph.D. thesis, University of
New South Wales, in press.

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