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([2001:a61:24d6:4e01:ef75:e978:47cd:1c50]) by smtp.gmail.com with ESMTPSA id a14sm423047wmm.44.2019.09.23.21.27.38 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 23 Sep 2019 21:27:39 -0700 (PDT) Cc: mtk.manpages@gmail.com, linux-man@vger.kernel.org, benh@kernel.crashing.org, mpe@ellerman.id.au Subject: Re: [PATCH] getauxval.3: Add new cache geometry entries To: Raphael Moreira Zinsly References: <20190916184136.13621-1-rzinsly@linux.vnet.ibm.com> From: "Michael Kerrisk (man-pages)" Message-ID: <9f0ee256-bc65-c850-a8ae-a833ca7a124d@gmail.com> Date: Tue, 24 Sep 2019 06:27:36 +0200 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:60.0) Gecko/20100101 Thunderbird/60.6.1 MIME-Version: 1.0 In-Reply-To: <20190916184136.13621-1-rzinsly@linux.vnet.ibm.com> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 7bit Sender: linux-man-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-man@vger.kernel.org Hello Raphael, On 9/16/19 8:41 PM, Raphael Moreira Zinsly wrote: > Add entries for the new cache geometry values of the auxiliary vectors > that got included in the kernel. > > Signed-off-by: Raphael Moreira Zinsly > --- > man3/getauxval.3 | 27 +++++++++++++++++++++++++++ > 1 file changed, 27 insertions(+) > > diff --git a/man3/getauxval.3 b/man3/getauxval.3 > index 794bc97b5..30f0757b5 100644 > --- a/man3/getauxval.3 > +++ b/man3/getauxval.3 > @@ -123,6 +123,33 @@ The instruction cache block size. > .\" .TP > .\" .BR AT_NOTELF > .TP > +.\" Kernel commit 98a5f361b8625c6f4841d6ba013bbf0e80d08147 > +.BR AT_L1D_CACHEGEOMETRY > +Geometry of the L1 data cache, that is, line size and number > +of ways. Thanks for the clarification of "ways" in you other mail. So, I think what could be added here is how these two pieces of information are encoded into the value. Could you add a sentence here? The other CACHEGEOMETRY entries could then just have a sentence "Encoded as for AT_L1D_CACHEGEOMETRY." Thanks, Michael > +.TP > +.BR AT_L1D_CACHESIZE > +The L1 data cache size. > +.TP > +.BR AT_L1I_CACHEGEOMETRY > +Geometry of the L1 instruction cache, that is, line size and > +number of ways. > +.TP > +.BR AT_L1I_CACHESIZE > +The L1 instruction cache size. > +.TP > +.BR AT_L2_CACHEGEOMETRY > +Geometry of the L2 cache, that is, line size and number of ways. > +.TP > +.BR AT_L2_CACHESIZE > +The L2 cache size. > +.TP > +.BR AT_L3_CACHEGEOMETRY > +Geometry of the L3 cache, that is, line size and number of ways. > +.TP > +.BR AT_L3_CACHESIZE > +The L3 cache size. > +.TP > .BR AT_PAGESZ > The system page size (the same value returned by > .IR sysconf(_SC_PAGESIZE) ). > -- Michael Kerrisk Linux man-pages maintainer; http://www.kernel.org/doc/man-pages/ Linux/UNIX System Programming Training: http://man7.org/training/