From mboxrd@z Thu Jan 1 00:00:00 1970 Return-path: Received: from metis.ext.4.pengutronix.de ([92.198.50.35]:54054 "EHLO metis.ext.4.pengutronix.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1755043AbcJNRfE (ORCPT ); Fri, 14 Oct 2016 13:35:04 -0400 From: Philipp Zabel To: linux-media@vger.kernel.org Cc: Steve Longerbeam , Marek Vasut , Hans Verkuil , Gary Bisson , kernel@pengutronix.de, Philipp Zabel Subject: [PATCH v2 14/21] ARM: dts: imx6qdl: Add MIPI CSI-2 D-PHY compatible and clocks Date: Fri, 14 Oct 2016 19:34:34 +0200 Message-Id: <1476466481-24030-15-git-send-email-p.zabel@pengutronix.de> In-Reply-To: <1476466481-24030-1-git-send-email-p.zabel@pengutronix.de> References: <1476466481-24030-1-git-send-email-p.zabel@pengutronix.de> Sender: linux-media-owner@vger.kernel.org List-ID: >>From the data sheets it is not quite clear what the clock inputs should be named, but freescale code calls them "dphy_clk" (would that be per?) and "pixel_clk" and connects them to the mipi_core_cfg and emi_podf clocks, respectively. The mipi_core_cfg control is called hsi_tx currently, but it really gates a whole lot of other clocks, too. Signed-off-by: Philipp Zabel --- arch/arm/boot/dts/imx6qdl.dtsi | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/arm/boot/dts/imx6qdl.dtsi b/arch/arm/boot/dts/imx6qdl.dtsi index cd325bd..2be6de4 100644 --- a/arch/arm/boot/dts/imx6qdl.dtsi +++ b/arch/arm/boot/dts/imx6qdl.dtsi @@ -1123,9 +1123,16 @@ }; mipi_csi: mipi@021dc000 { + compatible = "fsl,imx6q-mipi-csi2", "dw-mipi-csi2"; reg = <0x021dc000 0x4000>; + clocks = <&clks IMX6QDL_CLK_HSI_TX>, /* mipi_core_cfg/ipg_clk_root */ + <&clks IMX6QDL_CLK_HSI_TX>, /* mipi_core_cfg/video_27m_clk_root */ + <&clks IMX6QDL_CLK_HSI_TX>, /* mipi_core_cfg/video_27m_clk_root */ + <&clks IMX6QDL_CLK_EIM_PODF>; /* shoid be ipu1_ipu_hsp_clk_root on S/DL, axi_clk_root on D/Q */ + clock-names = "pclk", "cfg", "ref", "pixel"; #address-cells = <1>; #size-cells = <0>; + status = "disabled"; }; mipi_dsi: mipi@021e0000 { -- 2.9.3