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From: Yong Zhi <yong.zhi@intel.com>
To: linux-media@vger.kernel.org, sakari.ailus@linux.intel.com
Cc: tfiga@chromium.org, rajmohan.mani@intel.com,
	tuukka.toivonen@intel.com, jerry.w.hu@intel.com,
	tian.shu.qiu@intel.com, laurent.pinchart@ideasonboard.com,
	hans.verkuil@cisco.com, mchehab@kernel.org, bingbu.cao@intel.com,
	jian.xu.zheng@intel.com, Yong Zhi <yong.zhi@intel.com>
Subject: [PATCH v8 05/17] media: staging/intel-ipu3: css: Add dma buff pool utility functions
Date: Thu,  6 Dec 2018 19:03:30 -0600	[thread overview]
Message-ID: <1544144622-29791-6-git-send-email-yong.zhi@intel.com> (raw)
In-Reply-To: <1544144622-29791-1-git-send-email-yong.zhi@intel.com>

The pools are used to store previous parameters set by
user with the parameter queue. Due to pipelining,
there needs to be multiple sets (up to four)
of parameters which are queued in a host-to-sp queue.

Signed-off-by: Yong Zhi <yong.zhi@intel.com>
---
 drivers/staging/media/ipu3/ipu3-css-pool.c | 100 +++++++++++++++++++++++++++++
 drivers/staging/media/ipu3/ipu3-css-pool.h |  55 ++++++++++++++++
 2 files changed, 155 insertions(+)
 create mode 100644 drivers/staging/media/ipu3/ipu3-css-pool.c
 create mode 100644 drivers/staging/media/ipu3/ipu3-css-pool.h

diff --git a/drivers/staging/media/ipu3/ipu3-css-pool.c b/drivers/staging/media/ipu3/ipu3-css-pool.c
new file mode 100644
index 000000000000..6f271f81669b
--- /dev/null
+++ b/drivers/staging/media/ipu3/ipu3-css-pool.c
@@ -0,0 +1,100 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2018 Intel Corporation
+
+#include <linux/device.h>
+
+#include "ipu3.h"
+#include "ipu3-css-pool.h"
+#include "ipu3-dmamap.h"
+
+int ipu3_css_dma_buffer_resize(struct imgu_device *imgu,
+			       struct ipu3_css_map *map, size_t size)
+{
+	if (map->size < size && map->vaddr) {
+		dev_warn(&imgu->pci_dev->dev, "dma buf resized from %zu to %zu",
+			 map->size, size);
+
+		ipu3_dmamap_free(imgu, map);
+		if (!ipu3_dmamap_alloc(imgu, map, size))
+			return -ENOMEM;
+	}
+
+	return 0;
+}
+
+void ipu3_css_pool_cleanup(struct imgu_device *imgu, struct ipu3_css_pool *pool)
+{
+	unsigned int i;
+
+	for (i = 0; i < IPU3_CSS_POOL_SIZE; i++)
+		ipu3_dmamap_free(imgu, &pool->entry[i].param);
+}
+
+int ipu3_css_pool_init(struct imgu_device *imgu, struct ipu3_css_pool *pool,
+		       size_t size)
+{
+	unsigned int i;
+
+	for (i = 0; i < IPU3_CSS_POOL_SIZE; i++) {
+		pool->entry[i].valid = false;
+		if (size == 0) {
+			pool->entry[i].param.vaddr = NULL;
+			continue;
+		}
+
+		if (!ipu3_dmamap_alloc(imgu, &pool->entry[i].param, size))
+			goto fail;
+	}
+
+	pool->last = IPU3_CSS_POOL_SIZE;
+
+	return 0;
+
+fail:
+	ipu3_css_pool_cleanup(imgu, pool);
+	return -ENOMEM;
+}
+
+/*
+ * Allocate a new parameter via recycling the oldest entry in the pool.
+ */
+void ipu3_css_pool_get(struct ipu3_css_pool *pool)
+{
+	/* Get the oldest entry */
+	u32 n = (pool->last + 1) % IPU3_CSS_POOL_SIZE;
+
+	pool->entry[n].valid = true;
+	pool->last = n;
+}
+
+/*
+ * Undo, for all practical purposes, the effect of pool_get().
+ */
+void ipu3_css_pool_put(struct ipu3_css_pool *pool)
+{
+	pool->entry[pool->last].valid = false;
+	pool->last = (pool->last + IPU3_CSS_POOL_SIZE - 1) % IPU3_CSS_POOL_SIZE;
+}
+
+/**
+ * ipu3_css_pool_last - Retrieve the nth pool entry from last
+ *
+ * @pool: a pointer to &struct ipu3_css_pool.
+ * @n: the distance to the last index.
+ *
+ * Returns:
+ *  The nth entry from last or null map to indicate no frame stored.
+ */
+const struct ipu3_css_map *
+ipu3_css_pool_last(struct ipu3_css_pool *pool, unsigned int n)
+{
+	static const struct ipu3_css_map null_map = { 0 };
+	int i = (pool->last + IPU3_CSS_POOL_SIZE - n) % IPU3_CSS_POOL_SIZE;
+
+	WARN_ON(n >= IPU3_CSS_POOL_SIZE);
+
+	if (!pool->entry[i].valid)
+		return &null_map;
+
+	return &pool->entry[i].param;
+}
diff --git a/drivers/staging/media/ipu3/ipu3-css-pool.h b/drivers/staging/media/ipu3/ipu3-css-pool.h
new file mode 100644
index 000000000000..9c895efd2bfa
--- /dev/null
+++ b/drivers/staging/media/ipu3/ipu3-css-pool.h
@@ -0,0 +1,55 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/* Copyright (C) 2018 Intel Corporation */
+
+#ifndef __IPU3_UTIL_H
+#define __IPU3_UTIL_H
+
+struct device;
+struct imgu_device;
+
+#define IPU3_CSS_POOL_SIZE		4
+
+/**
+ * ipu3_css_map - store DMA mapping info for buffer
+ *
+ * @size:		size of the buffer in bytes.
+ * @vaddr:		kernel virtual address.
+ * @daddr:		iova dma address to access IPU3.
+ * @vma:		private, a pointer to &struct vm_struct,
+ * 			used for ipu3_dmamap_free.
+ */
+struct ipu3_css_map {
+	size_t size;
+	void *vaddr;
+	dma_addr_t daddr;
+	struct vm_struct *vma;
+};
+
+/**
+ * ipu3_css_pool - circular buffer pool definition
+ *
+ * @entry:		array with IPU3_CSS_POOL_SIZE elements.
+ * @entry.param:	a &struct ipu3_css_map for storing the mem mapping.
+ * @entry.valid:	used to mark if the entry has vaid data.
+ * @last:		write pointer, initialized to IPU3_CSS_POOL_SIZE.
+ */
+struct ipu3_css_pool {
+	struct {
+		struct ipu3_css_map param;
+		bool valid;
+	} entry[IPU3_CSS_POOL_SIZE];
+	u32 last;
+};
+
+int ipu3_css_dma_buffer_resize(struct imgu_device *imgu,
+			       struct ipu3_css_map *map, size_t size);
+void ipu3_css_pool_cleanup(struct imgu_device *imgu,
+			   struct ipu3_css_pool *pool);
+int ipu3_css_pool_init(struct imgu_device *imgu, struct ipu3_css_pool *pool,
+		       size_t size);
+void ipu3_css_pool_get(struct ipu3_css_pool *pool);
+void ipu3_css_pool_put(struct ipu3_css_pool *pool);
+const struct ipu3_css_map *ipu3_css_pool_last(struct ipu3_css_pool *pool,
+					      u32 last);
+
+#endif
-- 
2.7.4


  parent reply	other threads:[~2018-12-07  1:04 UTC|newest]

Thread overview: 25+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-12-07  1:03 [PATCH v8 00/17] Intel IPU3 ImgU patchset Yong Zhi
2018-12-07  1:03 ` [PATCH v8 01/17] media: staging/intel-ipu3: abi: Add register definitions and enum Yong Zhi
2018-12-07  1:03 ` [PATCH v8 02/17] media: staging/intel-ipu3: abi: Add structs Yong Zhi
2018-12-07  1:03 ` [PATCH v8 03/17] media: staging/intel-ipu3: mmu: Implement driver Yong Zhi
2018-12-07  1:03 ` [PATCH v8 04/17] media: staging/intel-ipu3: Implement DMA mapping functions Yong Zhi
2018-12-07  1:03 ` Yong Zhi [this message]
2018-12-07  1:03 ` [PATCH v8 06/17] media: staging/intel-ipu3: css: Add support for firmware management Yong Zhi
2018-12-07  1:03 ` [PATCH v8 08/17] media: staging/intel-ipu3: css: Compute and program ccs Yong Zhi
2018-12-07  1:03 ` [PATCH v8 10/17] media: staging/intel-ipu3: Add css pipeline programming Yong Zhi
2018-12-07  1:03 ` [PATCH v8 11/17] media: staging/intel-ipu3: Add v4l2 driver based on media framework Yong Zhi
2018-12-07  1:03 ` [PATCH v8 12/17] media: staging/intel-ipu3: Add imgu top level pci device driver Yong Zhi
2018-12-07  1:03 ` [PATCH v8 13/17] media: staging/intel-ipu3: Add Intel IPU3 meta data uAPI Yong Zhi
2018-12-07  1:03 ` [PATCH v8 14/17] media: staging/intel-ipu3: Add dual pipe support Yong Zhi
2018-12-07  1:03 ` [PATCH v8 15/17] media: v4l: Add Intel IPU3 meta buffer formats Yong Zhi
2018-12-11 12:58   ` Laurent Pinchart
2019-01-10 12:29     ` Laurent Pinchart
2019-01-10 18:35     ` Zhi, Yong
2019-01-22 21:22       ` Laurent Pinchart
2019-01-22 21:46         ` Zhi, Yong
2018-12-07  1:03 ` [PATCH v8 16/17] media: v4l2-ctrls: Reserve controls for IPU3 ImgU Yong Zhi
2018-12-07  1:03 ` [PATCH v8 17/17] doc-rst: Add Intel IPU3 documentation Yong Zhi
2018-12-09 22:33   ` Sakari Ailus
2018-12-11 13:04   ` Laurent Pinchart
2018-12-14 11:02   ` Mauro Carvalho Chehab
2018-12-10 21:07 ` [PATCH v8 00/17] Intel IPU3 ImgU patchset sakari.ailus

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