From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.9 required=3.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH, MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2CAABC54FD6 for ; Mon, 23 Mar 2020 17:53:13 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 037032072E for ; Mon, 23 Mar 2020 17:53:13 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=nvidia.com header.i=@nvidia.com header.b="pq90Ds+n" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727635AbgCWRwl (ORCPT ); Mon, 23 Mar 2020 13:52:41 -0400 Received: from hqnvemgate24.nvidia.com ([216.228.121.143]:17081 "EHLO hqnvemgate24.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727285AbgCWRwk (ORCPT ); Mon, 23 Mar 2020 13:52:40 -0400 Received: from hqpgpgate102.nvidia.com (Not Verified[216.228.121.13]) by hqnvemgate24.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Mon, 23 Mar 2020 10:51:10 -0700 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate102.nvidia.com (PGP Universal service); Mon, 23 Mar 2020 10:52:39 -0700 X-PGP-Universal: processed; by hqpgpgate102.nvidia.com on Mon, 23 Mar 2020 10:52:39 -0700 Received: from HQMAIL105.nvidia.com (172.20.187.12) by HQMAIL109.nvidia.com (172.20.187.15) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Mon, 23 Mar 2020 17:52:38 +0000 Received: from hqnvemgw03.nvidia.com (10.124.88.68) by HQMAIL105.nvidia.com (172.20.187.12) with Microsoft SMTP Server (TLS) id 15.0.1473.3 via Frontend Transport; Mon, 23 Mar 2020 17:52:38 +0000 Received: from skomatineni-linux.nvidia.com (Not Verified[10.2.160.78]) by hqnvemgw03.nvidia.com with Trustwave SEG (v7,5,8,10121) id ; Mon, 23 Mar 2020 10:52:38 -0700 From: Sowjanya Komatineni To: , , , , , CC: , , , , , , Subject: [RFC PATCH v5 3/9] dt-bindings: clock: tegra: Add clk id for CSI TPG clock Date: Mon, 23 Mar 2020 10:52:29 -0700 Message-ID: <1584985955-19101-4-git-send-email-skomatineni@nvidia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1584985955-19101-1-git-send-email-skomatineni@nvidia.com> References: <1584985955-19101-1-git-send-email-skomatineni@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 Content-Type: text/plain DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1584985870; bh=FfGJH9b8JGj6Sguul3LNMexpCVjUbOXcObIX96zc9Fo=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:X-NVConfidentiality:MIME-Version: Content-Type; b=pq90Ds+nyk/TCmUgYBYAHZhByLKp9/zqtgbi6kGFp7w8m37QQOrYaXRgfBg/pVD/1 RU2PZJik6E6AMu6UGvEN0LUhdziEW20hpdKbmDIGpFobQryy6a6+C4FBS6YWEa8QA0 34Bguu/oNK3wcSlOA3Dg6rVVrPOElh1s2mYuNisS+GspFOBRqIZIGj1IC2nRspr5l8 /0Pns7bRiIblAQiuJyuLyW5HU5TzMJql2SRqcYXFf/FwqrOu6hBmiMY+DGbyJieZIG 6L1avABQ3EUhhvzWwvn41ZXyi3yQ/DmELJlaSa3LIbDlCUeqq59wl15BM8tWkv8C21 bHsSm6ZjMysPw== Sender: linux-media-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org Tegra210 uses PLLD out internally for CSI TPG. This patch adds clk id for this CSI TPG clock from PLLD. Acked-by: Stephen Boyd Signed-off-by: Sowjanya Komatineni --- include/dt-bindings/clock/tegra210-car.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/dt-bindings/clock/tegra210-car.h b/include/dt-bindings/clock/tegra210-car.h index 7a8f10b..d8909e0 100644 --- a/include/dt-bindings/clock/tegra210-car.h +++ b/include/dt-bindings/clock/tegra210-car.h @@ -351,7 +351,7 @@ #define TEGRA210_CLK_PLL_P_OUT_XUSB 317 #define TEGRA210_CLK_XUSB_SSP_SRC 318 #define TEGRA210_CLK_PLL_RE_OUT1 319 -/* 320 */ +#define TEGRA210_CLK_CSI_TPG 320 /* 321 */ #define TEGRA210_CLK_ISP 322 #define TEGRA210_CLK_PLL_A_OUT_ADSP 323 -- 2.7.4