Hi, On Tue, Apr 09, 2019 at 12:57:42AM +0800, Chen-Yu Tsai wrote: > From: Chen-Yu Tsai > > The A83T SoC has a camera sensor interface (known as CSI in Allwinner > lingo), which is similar to the one found on the A64 and H3. The only > difference seems to be that support of MIPI CSI through a connected > MIPI CSI-2 bridge. > > Add a device node for it, and pinctrl nodes for the commonly used MCLK > and 8-bit parallel interface. The property /omit-if-no-ref/ is added to > the pinctrl nodes to keep the device tree blob size down if they are > unused. > > Signed-off-by: Chen-Yu Tsai > --- > arch/arm/boot/dts/sun8i-a83t.dtsi | 31 +++++++++++++++++++++++++++++++ > 1 file changed, 31 insertions(+) > > diff --git a/arch/arm/boot/dts/sun8i-a83t.dtsi b/arch/arm/boot/dts/sun8i-a83t.dtsi > index f739b88efb53..0c52f945fd5f 100644 > --- a/arch/arm/boot/dts/sun8i-a83t.dtsi > +++ b/arch/arm/boot/dts/sun8i-a83t.dtsi > @@ -682,6 +682,20 @@ > #interrupt-cells = <3>; > #gpio-cells = <3>; > > + /omit-if-no-ref/ > + csi_8bit_parallel_pins: csi-8bit-parallel-pins { > + pins = "PE0", "PE2", "PE3", "PE6", "PE7", > + "PE8", "PE9", "PE10", "PE11", > + "PE12", "PE13"; > + function = "csi"; > + }; > + > + /omit-if-no-ref/ > + csi_mclk_pin: csi-mclk-pin { > + pins = "PE1"; > + function = "csi"; > + }; > + > emac_rgmii_pins: emac-rgmii-pins { > pins = "PD2", "PD3", "PD4", "PD5", "PD6", "PD7", > "PD11", "PD12", "PD13", "PD14", "PD18", > @@ -994,6 +1008,23 @@ > interrupts = ; > }; > > + csi: camera@1cb0000 { > + compatible = "allwinner,sun8i-a83t-csi"; > + reg = <0x01cb0000 0x1000>; > + interrupts = ; > + clocks = <&ccu CLK_BUS_CSI>, > + <&ccu CLK_CSI_SCLK>, > + <&ccu CLK_DRAM_CSI>; > + clock-names = "bus", "mod", "ram"; > + resets = <&ccu RST_BUS_CSI>; > + status = "disabled"; > + > + csi_in: port { > + #address-cells = <1>; > + #size-cells = <0>; If we expect a single enpoint, then we don't need the address-cells and size-cells properties. Maxime -- Maxime Ripard, Bootlin Embedded Linux and Kernel engineering https://bootlin.com