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From: Yong <yong.deng@magewell.com>
To: megous@megous.com
Cc: linux-sunxi@googlegroups.com,
	Mauro Carvalho Chehab <mchehab@kernel.org>,
	Maxime Ripard <mripard@kernel.org>, Chen-Yu Tsai <wens@csie.org>,
	linux-media@vger.kernel.org (open list:CSI DRIVERS FOR ALLWINNER
	V3s),
	linux-arm-kernel@lists.infradead.org (moderated
	list:ARM/Allwinner sunXi SoC support),
	linux-kernel@vger.kernel.org (open list)
Subject: Re: [linux-sunxi] [PATCH] media: sun6i-csi: Fix incorrect HSYNC/VSYNC/PCLK polarity configuration
Date: Thu, 28 Nov 2019 10:26:08 +0800	[thread overview]
Message-ID: <20191128102608.035cbb996c8681a6fb035336@magewell.com> (raw)
In-Reply-To: <20191128020259.1338188-1-megous@megous.com>

Hi Ondrej,

This has been discussed.
And Maxime sent a patch for this: 
https://www.mail-archive.com/linux-media@vger.kernel.org/msg127149.html

On Thu, 28 Nov 2019 03:02:59 +0100
Ondrej Jirman <megous@megous.com> wrote:

> This was discovered by writing a new camera driver and wondering, why
> hsync/vsync polarity setting behaves in reverse to what would be
> expected. Verified by looking at the actual signals and the SoC
> user manual.
> 
> Fixes: 5cc7522d8965 ("media: sun6i: Add support for Allwinner CSI V3s")
> Signed-off-by: Ondrej Jirman <megous@megous.com>
> ---
>  drivers/media/platform/sunxi/sun6i-csi/sun6i_csi.c | 6 +++---
>  1 file changed, 3 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/media/platform/sunxi/sun6i-csi/sun6i_csi.c b/drivers/media/platform/sunxi/sun6i-csi/sun6i_csi.c
> index f17e5550602d..98bbcca59a90 100644
> --- a/drivers/media/platform/sunxi/sun6i-csi/sun6i_csi.c
> +++ b/drivers/media/platform/sunxi/sun6i-csi/sun6i_csi.c
> @@ -417,12 +417,12 @@ static void sun6i_csi_setup_bus(struct sun6i_csi_dev *sdev)
>  		if (flags & V4L2_MBUS_FIELD_EVEN_LOW)
>  			cfg |= CSI_IF_CFG_FIELD_POSITIVE;
>  
> -		if (flags & V4L2_MBUS_VSYNC_ACTIVE_LOW)
> +		if (flags & V4L2_MBUS_VSYNC_ACTIVE_HIGH)
>  			cfg |= CSI_IF_CFG_VREF_POL_POSITIVE;
> -		if (flags & V4L2_MBUS_HSYNC_ACTIVE_LOW)
> +		if (flags & V4L2_MBUS_HSYNC_ACTIVE_HIGH)
>  			cfg |= CSI_IF_CFG_HREF_POL_POSITIVE;
>  
> -		if (flags & V4L2_MBUS_PCLK_SAMPLE_RISING)
> +		if (flags & V4L2_MBUS_PCLK_SAMPLE_FALLING)
>  			cfg |= CSI_IF_CFG_CLK_POL_FALLING_EDGE;
>  		break;
>  	case V4L2_MBUS_BT656:
> -- 
> 2.24.0
> 
> -- 
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> To view this discussion on the web, visit https://groups.google.com/d/msgid/linux-sunxi/20191128020259.1338188-1-megous%40megous.com.


Thanks,
Yong

  reply	other threads:[~2019-11-28  2:26 UTC|newest]

Thread overview: 6+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-11-28  2:02 [PATCH] media: sun6i-csi: Fix incorrect HSYNC/VSYNC/PCLK polarity configuration Ondrej Jirman
2019-11-28  2:26 ` Yong [this message]
2019-11-28  3:06   ` [linux-sunxi] " Ondřej Jirman
2019-11-28  3:26     ` Chen-Yu Tsai
2019-11-28  3:50       ` Ondřej Jirman
2019-11-28  4:14         ` Chen-Yu Tsai

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