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[46.91.239.63]) by smtp.gmail.com with ESMTPSA id w13sm2118757wru.38.2020.01.29.01.46.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 29 Jan 2020 01:46:25 -0800 (PST) Date: Wed, 29 Jan 2020 10:46:24 +0100 From: Thierry Reding To: Sowjanya Komatineni Cc: jonathanh@nvidia.com, frankc@nvidia.com, hverkuil@xs4all.nl, linux-media@vger.kernel.org, devicetree@vger.kernel.org, linux-clk@vger.kernel.org, linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org Subject: Re: [RFC PATCH v1 5/5] arm64: tegra: Add Tegra VI CSI suppport in device tree Message-ID: <20200129094624.GD2479935@ulmo> References: <1580235801-4129-1-git-send-email-skomatineni@nvidia.com> <1580235801-4129-6-git-send-email-skomatineni@nvidia.com> MIME-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha256; protocol="application/pgp-signature"; boundary="SO98HVl1bnMOfKZd" Content-Disposition: inline In-Reply-To: <1580235801-4129-6-git-send-email-skomatineni@nvidia.com> User-Agent: Mutt/1.13.1 (2019-12-14) Sender: linux-media-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org --SO98HVl1bnMOfKZd Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Content-Transfer-Encoding: quoted-printable On Tue, Jan 28, 2020 at 10:23:21AM -0800, Sowjanya Komatineni wrote: > Tegra210 contains VI controller for video input capture from MIPI > CSI camera sensors and also supports built-in test pattern generator. >=20 > CSI ports can be one-to-one mapped to VI channels for capturing from > an external sensor or from built-in test pattern generator. >=20 > This patch adds support for VI and CSI and enables them in Tegra210 > device tree. >=20 > Signed-off-by: Sowjanya Komatineni > --- > arch/arm64/boot/dts/nvidia/tegra210-p2597.dtsi | 8 +++++++ > arch/arm64/boot/dts/nvidia/tegra210.dtsi | 31 ++++++++++++++++++++= +++++- > 2 files changed, 38 insertions(+), 1 deletion(-) >=20 > diff --git a/arch/arm64/boot/dts/nvidia/tegra210-p2597.dtsi b/arch/arm64/= boot/dts/nvidia/tegra210-p2597.dtsi > index b0095072bc28..ec1b3033fa03 100644 > --- a/arch/arm64/boot/dts/nvidia/tegra210-p2597.dtsi > +++ b/arch/arm64/boot/dts/nvidia/tegra210-p2597.dtsi > @@ -10,6 +10,14 @@ > status =3D "okay"; > }; > =20 > + vi@54080000 { > + status =3D "okay"; > + }; > + > + csi@0x54080838 { > + status =3D "okay"; > + }; > + > sor@54580000 { > status =3D "okay"; > =20 > diff --git a/arch/arm64/boot/dts/nvidia/tegra210.dtsi b/arch/arm64/boot/d= ts/nvidia/tegra210.dtsi > index 48c63256ba7f..c6107ec03ad1 100644 > --- a/arch/arm64/boot/dts/nvidia/tegra210.dtsi > +++ b/arch/arm64/boot/dts/nvidia/tegra210.dtsi > @@ -136,9 +136,38 @@ > =20 > vi@54080000 { > compatible =3D "nvidia,tegra210-vi"; > - reg =3D <0x0 0x54080000 0x0 0x00040000>; > + reg =3D <0x0 0x54080000 0x0 0x808>; > interrupts =3D ; > status =3D "disabled"; > + assigned-clocks =3D <&tegra_car TEGRA210_CLK_VI>; > + assigned-clock-parents =3D <&tegra_car TEGRA210_CLK_PLL_C4_OUT0>; > + > + clocks =3D <&tegra_car TEGRA210_CLK_VI>; > + clock-names =3D "vi"; > + resets =3D <&tegra_car 20>; > + reset-names =3D "vi"; > + }; > + > + csi@0x54080838 { > + compatible =3D "nvidia,tegra210-csi"; > + reg =3D <0x0 0x54080838 0x0 0x2000>; > + status =3D "disabled"; > + assigned-clocks =3D <&tegra_car TEGRA210_CLK_CILAB>, > + <&tegra_car TEGRA210_CLK_CILCD>, > + <&tegra_car TEGRA210_CLK_CILE>; > + assigned-clock-parents =3D <&tegra_car TEGRA210_CLK_PLL_P>, > + <&tegra_car TEGRA210_CLK_PLL_P>, > + <&tegra_car TEGRA210_CLK_PLL_P>; > + assigned-clock-rates =3D <102000000>, > + <102000000>, > + <102000000>; > + > + clocks =3D <&tegra_car TEGRA210_CLK_CSI>, > + <&tegra_car TEGRA210_CLK_CILAB>, > + <&tegra_car TEGRA210_CLK_CILCD>, > + <&tegra_car TEGRA210_CLK_CILE>; > + clock-names =3D "csi", "cilab", "cilcd", "cile"; > + > }; Can this be a child of the vi node? Looking at the register ranges it seems like these are actually a single IP block. If they have separate blocks with clearly separate functionality, then it makes sense to have CSI be a child node of VI, though it may also be okay to merge both and have a single node with the driver doing all of the differentiation between what's VI and what's CSI. Looking at later chips, the split between VI and CSI is more explicit, so having the split in DT for Tegra210 may make sense for consistency. I know we've discussed this before, but for some reason I keep coming back to this. I'll go through the other patches to see if I can get a clearer picture of how this could all work together. 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