Re: [PATCH 02/14] phy: allwinner: phy-sun6i-mipi-dphy: Support D-PHY Rx mode for MIPI CSI-2

[Maxime Ripard <maxime@cerno.tech>]

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Hi,

On Tue, Oct 27, 2020 at 10:23:26AM +0100, Paul Kocialkowski wrote:
> On Mon 26 Oct 20, 16:38, Maxime Ripard wrote:
> > On Fri, Oct 23, 2020 at 07:45:34PM +0200, Paul Kocialkowski wrote:
> > > The Allwinner A31 D-PHY supports both Rx and Tx modes. While the latter
> > > is already supported and used for MIPI DSI this adds support for the
> > > former, to be used with MIPI CSI-2.
> > > 
> > > This implementation is inspired by the Allwinner BSP implementation.
> > 
> > Mentionning which BSP you took this from would be helpful
> 
> Sure! It's from the Github repo linked from https://linux-sunxi.org/V3s.
> Would you like that I mention this URL explicitly or would it be enough to
> mention "Allwinner's V3s Linux SDK" as they seem to call it?

Yeah, that would be great
> > > +static int sun6i_dphy_rx_power_on(struct sun6i_dphy *dphy)
> > > +{
> > > +	/* Physical clock rate is actually half of symbol rate with DDR. */
> > > +	unsigned long mipi_symbol_rate = dphy->config.hs_clk_rate;
> > > +	unsigned long dphy_clk_rate;
> > > +	unsigned int rx_dly;
> > > +	unsigned int lprst_dly;
> > > +	u32 value;
> > > +
> > > +	dphy_clk_rate = clk_get_rate(dphy->mod_clk);
> > > +	if (!dphy_clk_rate)
> > > +		return -1;
> > 
> > Returning -1 is weird here?
> 
> What do you think would be a more appropriate error code to return?
> It looks like some other drivers return -EINVAL when that happens (but many
> don't do the check).

Yeah, EINVAL at least is better than ENOPERM 

> > > +
> > > +	/* Hardcoded timing parameters from the Allwinner BSP. */
> > > +	regmap_write(dphy->regs, SUN6I_DPHY_RX_TIME0_REG,
> > > +		     SUN6I_DPHY_RX_TIME0_HS_RX_SYNC(255) |
> > > +		     SUN6I_DPHY_RX_TIME0_HS_RX_CLK_MISS(255) |
> > > +		     SUN6I_DPHY_RX_TIME0_LP_RX(255));
> > > +
> > > +	/*
> > > +	 * Formula from the Allwinner BSP, with hardcoded coefficients
> > > +	 * (probably internal divider/multiplier).
> > > +	 */
> > > +	rx_dly = 8 * (unsigned int)(dphy_clk_rate / (mipi_symbol_rate / 8));
> > > +
> > > +	/*
> > > +	 * The Allwinner BSP has an alternative formula for LP_RX_ULPS_WP:
> > > +	 * lp_ulps_wp_cnt = lp_ulps_wp_ms * lp_clk / 1000
> > > +	 * but does not use it and hardcodes 255 instead.
> > > +	 */
> > > +	regmap_write(dphy->regs, SUN6I_DPHY_RX_TIME1_REG,
> > > +		     SUN6I_DPHY_RX_TIME1_RX_DLY(rx_dly) |
> > > +		     SUN6I_DPHY_RX_TIME1_LP_RX_ULPS_WP(255));
> > > +
> > > +	/* HS_RX_ANA0 value is hardcoded in the Allwinner BSP. */
> > > +	regmap_write(dphy->regs, SUN6I_DPHY_RX_TIME2_REG,
> > > +		     SUN6I_DPHY_RX_TIME2_HS_RX_ANA0(4));
> > > +
> > > +	/*
> > > +	 * Formula from the Allwinner BSP, with hardcoded coefficients
> > > +	 * (probably internal divider/multiplier).
> > > +	 */
> > > +	lprst_dly = 4 * (unsigned int)(dphy_clk_rate / (mipi_symbol_rate / 2));
> > > +
> > > +	regmap_write(dphy->regs, SUN6I_DPHY_RX_TIME3_REG,
> > > +		     SUN6I_DPHY_RX_TIME3_LPRST_DLY(lprst_dly));
> > > +
> > > +	/* Analog parameters are hardcoded in the Allwinner BSP. */
> > > +	regmap_write(dphy->regs, SUN6I_DPHY_ANA0_REG,
> > > +		     SUN6I_DPHY_ANA0_REG_PWS |
> > > +		     SUN6I_DPHY_ANA0_REG_SLV(7) |
> > > +		     SUN6I_DPHY_ANA0_REG_SFB(2));
> > > +
> > > +	regmap_write(dphy->regs, SUN6I_DPHY_ANA1_REG,
> > > +		     SUN6I_DPHY_ANA1_REG_SVTT(4));
> > > +
> > > +	regmap_write(dphy->regs, SUN6I_DPHY_ANA4_REG,
> > > +		     SUN6I_DPHY_ANA4_REG_DMPLVC |
> > > +		     SUN6I_DPHY_ANA4_REG_DMPLVD(1));
> > > +
> > > +	regmap_write(dphy->regs, SUN6I_DPHY_ANA2_REG,
> > > +		     SUN6I_DPHY_ANA2_REG_ENIB);
> > > +
> > > +	regmap_write(dphy->regs, SUN6I_DPHY_ANA3_REG,
> > > +		     SUN6I_DPHY_ANA3_EN_LDOR |
> > > +		     SUN6I_DPHY_ANA3_EN_LDOC |
> > > +		     SUN6I_DPHY_ANA3_EN_LDOD);
> > > +
> > > +	/*
> > > +	 * Delay comes from the Allwinner BSP, likely for internal regulator
> > > +	 * ramp-up.
> > > +	 */
> > > +	udelay(3);
> > > +
> > > +	value = SUN6I_DPHY_RX_CTL_EN_DBC | SUN6I_DPHY_RX_CTL_RX_CLK_FORCE;
> > > +
> > > +	/*
> > > +	 * Rx data lane force-enable bits are used as regular RX enable by the
> > > +	 * Allwinner BSP.
> > > +	 */
> > > +	if (dphy->config.lanes >= 1)
> > > +		value |= SUN6I_DPHY_RX_CTL_RX_D0_FORCE;
> > > +	if (dphy->config.lanes >= 2)
> > > +		value |= SUN6I_DPHY_RX_CTL_RX_D1_FORCE;
> > > +	if (dphy->config.lanes >= 3)
> > > +		value |= SUN6I_DPHY_RX_CTL_RX_D2_FORCE;
> > > +	if (dphy->config.lanes == 4)
> > > +		value |= SUN6I_DPHY_RX_CTL_RX_D3_FORCE;
> > > +
> > > +	regmap_write(dphy->regs, SUN6I_DPHY_RX_CTL_REG, value);
> > > +
> > > +	regmap_write(dphy->regs, SUN6I_DPHY_GCTL_REG,
> > > +		     SUN6I_DPHY_GCTL_LANE_NUM(dphy->config.lanes) |
> > > +		     SUN6I_DPHY_GCTL_EN);
> > > +
> > > +	return 0;
> > > +}
> > > +
> > > +static int sun6i_dphy_power_on(struct phy *phy)
> > > +{
> > > +	struct sun6i_dphy *dphy = phy_get_drvdata(phy);
> > > +
> > > +	switch (dphy->submode) {
> > > +	case PHY_MIPI_DPHY_SUBMODE_TX:
> > > +		return sun6i_dphy_tx_power_on(dphy);
> > > +	case PHY_MIPI_DPHY_SUBMODE_RX:
> > > +		return sun6i_dphy_rx_power_on(dphy);
> > > +	default:
> > > +		return -EINVAL;
> > > +	}
> > > +}
> > > +
> > 
> > Can one call power_on before set_mode?
> 
> I didn't find anything indicating this is illegal. What would happen here is
> that the D-PHY would be configured to PHY_MIPI_DPHY_SUBMODE_TX (submode == 0)
> at power-on if set_mode is not called before.
> 
> I think it's fair to expect that it's too late to change the mode once the PHY
> was powered on. Maybe we should return -EBUSY on set_mode when power on was
> already requested?

Or maybe we can just clarify it in the framework/function documentation

Maxime

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