From: Rob Herring <robh@kernel.org>
To: Ming Qian <ming.qian@nxp.com>
Cc: mchehab@kernel.org, shawnguo@kernel.org, s.hauer@pengutronix.de,
hverkuil-cisco@xs4all.nl, kernel@pengutronix.de,
festevam@gmail.com, linux-imx@nxp.com, aisheng.dong@nxp.com,
linux-media@vger.kernel.org, linux-kernel@vger.kernel.org,
devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org
Subject: Re: [PATCH v4 01/13] dt-bindings: media: imx8q: add imx video codec bindings
Date: Mon, 26 Jul 2021 16:36:26 -0600 [thread overview]
Message-ID: <20210726223626.GA991611@robh.at.kernel.org> (raw)
In-Reply-To: <5032168eca16a277cc8ba9e951073a37089c0eec.1626743758.git.ming.qian@nxp.com>
On Tue, Jul 20, 2021 at 09:43:20AM +0800, Ming Qian wrote:
> Add devicetree binding documentation for IMX8Q Video Processing Unit IP
>
> Signed-off-by: Ming Qian <ming.qian@nxp.com>
> Signed-off-by: Shijie Qin <shijie.qin@nxp.com>
> Signed-off-by: Zhou Peng <eagle.zhou@nxp.com>
> ---
> .../bindings/media/nxp,imx8q-vpu.yaml | 178 ++++++++++++++++++
> 1 file changed, 178 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/media/nxp,imx8q-vpu.yaml
>
> diff --git a/Documentation/devicetree/bindings/media/nxp,imx8q-vpu.yaml b/Documentation/devicetree/bindings/media/nxp,imx8q-vpu.yaml
> new file mode 100644
> index 000000000000..337c9bf2395f
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/media/nxp,imx8q-vpu.yaml
> @@ -0,0 +1,178 @@
> +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
> +
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/media/nxp,imx8q-vpu.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: NXP i.MX8Q video encode and decode accelerators
> +
> +maintainers:
> + - Ming Qian <ming.qian@nxp.com>
> + - Shijie Qin <shijie.qin@nxp.com>
> +
> +description: |-
> + The Amphion MXC video encoder(Windsor) and decoder(Malone) accelerators present
> + on NXP i.MX8Q SoCs.
> +
> +properties:
> + $nodename:
> + pattern: "^vpu@[0-9a-f]+$"
> +
> + compatible:
> + oneOf:
> + - const: nxp,imx8qm-vpu
> + - const: nxp,imx8qxp-vpu
> +
> + reg:
> + maxItems: 1
> +
> + power-domains:
> + maxItems: 1
> +
> + "#address-cells":
> + const: 1
> +
> + "#size-cells":
> + const: 1
> +
> + ranges: true
> +
> +patternProperties:
> + "^mailbox@[0-9a-f]+$":
> + description:
> + Each vpu encoder or decoder correspond a MU, which used for communication
> + between driver and firmware. Implement via mailbox on driver.
> + $ref: ../mailbox/fsl,mu.yaml#
> +
> +
> + "^vpu_core@[0-9a-f]+$":
> + description:
> + Each core correspond a decoder or encoder, need to configure them
> + separately. NXP i.MX8QM SoC has one decoder and two encoder, i.MX8QXP SoC
> + has one decoder and one encoder.
> + type: object
> +
> + properties:
> + compatible:
> + oneOf:
> + - const: nxp,imx8q-vpu-decoder
> + - const: nxp,imx8q-vpu-encoder
> +
> + reg:
> + maxItems: 1
> +
> + power-domains:
> + maxItems: 1
> +
> + mbox-names:
> + items:
> + - const: tx0
> + - const: tx1
> + - const: rx
3 here and...
> +
> + mboxes:
> + description:
> + List of phandle of 2 MU channels for tx, 1 MU channel for rx.
> + maxItems: 1
1 here?
> +
> + memory-region:
> + description:
> + Phandle to the reserved memory nodes to be associated with the
> + remoteproc device. The reserved memory nodes should be carveout nodes,
> + and should be defined as per the bindings in
> + Documentation/devicetree/bindings/reserved-memory/reserved-memory.txt
> + items:
> + - description: region reserved for firmware image sections.
> + - description: region used for RPC shared memory between firmware and
> + driver.
> +
> + required:
> + - compatible
> + - reg
> + - power-domains
> + - mbox-names
> + - mboxes
> + - memory-region
> +
> + additionalProperties: false
> +
> +required:
> + - compatible
> + - reg
> + - power-domains
> +
> +additionalProperties: false
> +
> +examples:
> + # Device node example for i.MX8QM platform:
> + - |
> + #include <dt-bindings/firmware/imx/rsrc.h>
> +
> + vpu: vpu@2c000000 {
> + compatible = "nxp,imx8qm-vpu";
> + ranges = <0x2c000000 0x2c000000 0x2000000>;
> + reg = <0x2c000000 0x1000000>;
> + #address-cells = <1>;
> + #size-cells = <1>;
> + power-domains = <&pd IMX_SC_R_VPU>;
> +
> + mu_m0: mailbox@2d000000 {
> + compatible = "fsl,imx6sx-mu";
> + reg = <0x2d000000 0x20000>;
> + interrupts = <0 472 4>;
> + #mbox-cells = <2>;
> + power-domains = <&pd IMX_SC_R_VPU_MU_0>;
> + };
> +
> + mu1_m0: mailbox@2d020000 {
> + compatible = "fsl,imx6sx-mu";
> + reg = <0x2d020000 0x20000>;
> + interrupts = <0 473 4>;
> + #mbox-cells = <2>;
> + power-domains = <&pd IMX_SC_R_VPU_MU_1>;
> + };
> +
> + mu2_m0: mailbox@2d040000 {
> + compatible = "fsl,imx6sx-mu";
> + reg = <0x2d040000 0x20000>;
> + interrupts = <0 474 4>;
> + #mbox-cells = <2>;
> + power-domains = <&pd IMX_SC_R_VPU_MU_2>;
> + };
> +
> + vpu_core0: vpu_core@2d080000 {
> + compatible = "nxp,imx8q-vpu-decoder";
> + reg = <0x2d080000 0x10000>;
> + power-domains = <&pd IMX_SC_R_VPU_DEC_0>;
> + mbox-names = "tx0", "tx1", "rx";
> + mboxes = <&mu_m0 0 0
> + &mu_m0 0 1
> + &mu_m0 1 0>;
> + memory-region = <&decoder_boot>, <&decoder_rpc>;
> + };
> +
> + vpu_core1: vpu_core@2d090000 {
> + compatible = "nxp,imx8q-vpu-encoder";
> + reg = <0x2d090000 0x10000>;
> + power-domains = <&pd IMX_SC_R_VPU_ENC_0>;
> + mbox-names = "tx0", "tx1", "rx";
> + mboxes = <&mu1_m0 0 0
> + &mu1_m0 0 1
> + &mu1_m0 1 0>;
> + memory-region = <&encoder1_boot>, <&encoder1_rpc>;
> + };
> +
> + vpu_core2: vpu_core@2d0a0000 {
> + reg = <0x2d0a0000 0x10000>;
> + compatible = "nxp,imx8q-vpu-encoder";
> + power-domains = <&pd IMX_SC_R_VPU_ENC_1>;
> + mbox-names = "tx0", "tx1", "rx";
> + mboxes = <&mu2_m0 0 0
> + &mu2_m0 0 1
> + &mu2_m0 1 0>;
> + memory-region = <&encoder2_boot>, <&encoder2_rpc>;
> + };
> + };
> +
> +...
> --
> 2.32.0
>
>
next prev parent reply other threads:[~2021-07-26 22:36 UTC|newest]
Thread overview: 20+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-07-20 1:43 [PATCH v4 00/13] imx8q video decoder/encoder driver Ming Qian
2021-07-20 1:43 ` [PATCH v4 01/13] dt-bindings: media: imx8q: add imx video codec bindings Ming Qian
2021-07-26 22:36 ` Rob Herring [this message]
2021-07-20 1:43 ` [PATCH v4 02/13] media: v4l: add some definition of v4l2 colorspace/xfer_func/ycbcr_encoding Ming Qian
2021-07-21 10:09 ` Hans Verkuil
2021-07-20 1:43 ` [PATCH v4 03/13] media: imx: imx8q: add imx8q vpu device driver Ming Qian
2021-07-21 7:47 ` Hans Verkuil
2021-07-20 1:43 ` [PATCH v4 04/13] media: imx: imx8q: add vpu core driver Ming Qian
2021-07-20 1:43 ` [PATCH v4 05/13] media: imx: imx8q: implement vpu core communication based on mailbox Ming Qian
2021-07-20 1:43 ` [PATCH v4 06/13] media: imx: imx8q: add vpu v4l2 m2m support Ming Qian
2021-07-20 1:43 ` [PATCH v4 07/13] media: imx: imx8q: add v4l2 m2m vpu encoder stateful driver Ming Qian
2021-07-20 1:43 ` [PATCH v4 08/13] media: imx: imx8q: add v4l2 m2m vpu decoder " Ming Qian
2021-07-20 1:43 ` [PATCH v4 09/13] media: imx: imx8q: implement windsor encoder rpc interface Ming Qian
2021-07-20 1:43 ` [PATCH v4 10/13] media: imx: imx8q: implement malone decoder " Ming Qian
2021-07-20 1:43 ` [PATCH v4 11/13] ARM64: dts: freescale: imx8q: add imx vpu codec entries Ming Qian
2021-07-20 1:43 ` [PATCH v4 12/13] firmware: imx: scu-pd: imx8q: add vpu mu resources Ming Qian
2021-07-20 1:43 ` [PATCH v4 13/13] MAINTAINERS: add NXP IMX8Q VPU CODEC V4L2 driver entry Ming Qian
2021-07-21 7:33 ` [PATCH v4 00/13] imx8q video decoder/encoder driver Hans Verkuil
2021-07-21 8:53 ` [EXT] " Ming Qian
2021-07-21 9:38 ` Hans Verkuil
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