From: Yunfei Dong <yunfei.dong@mediatek.com>
To: Yunfei Dong <yunfei.dong@mediatek.com>,
Alexandre Courbot <acourbot@chromium.org>,
Hans Verkuil <hverkuil-cisco@xs4all.nl>,
Tzung-Bi Shih <tzungbi@chromium.org>,
Tiffany Lin <tiffany.lin@mediatek.com>,
Andrew-CT Chen <andrew-ct.chen@mediatek.com>,
Mauro Carvalho Chehab <mchehab@kernel.org>,
Rob Herring <robh+dt@kernel.org>,
Matthias Brugger <matthias.bgg@gmail.com>,
Tomasz Figa <tfiga@google.com>,
Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Cc: Daniel Vetter <daniel@ffwll.ch>,
dri-devel <dri-devel@lists.freedesktop.org>,
Hsin-Yi Wang <hsinyi@chromium.org>,
Fritz Koenig <frkoenig@chromium.org>,
Irui Wang <irui.wang@mediatek.com>, <linux-media@vger.kernel.org>,
<devicetree@vger.kernel.org>, <linux-kernel@vger.kernel.org>,
<linux-arm-kernel@lists.infradead.org>,
<srv_heupstream@mediatek.com>,
<linux-mediatek@lists.infradead.org>,
<Project_Global_Chrome_Upstream_Group@mediatek.com>
Subject: [PATCH v6, 13/15] dt-bindings: media: mtk-vcodec: Adds decoder dt-bindings for mt8192
Date: Wed, 1 Sep 2021 16:32:13 +0800 [thread overview]
Message-ID: <20210901083215.25984-14-yunfei.dong@mediatek.com> (raw)
In-Reply-To: <20210901083215.25984-1-yunfei.dong@mediatek.com>
Adds decoder dt-bindings for mt8192.
Signed-off-by: Yunfei Dong <yunfei.dong@mediatek.com>
---
v6: add decoder block diagram for Laurent's comments.
This patch depends on "Mediatek MT8192 clock support"[1].
The definition of decoder clocks are in mt8192-clk.h, and this patch already in clk tree[1].
[1]https://git.kernel.org/pub/scm/linux/kernel/git/clk/linux.git/commit/?h=clk-next&id=f35f1a23e0e12e3173e9e9dedbc150d139027189
---
.../media/mediatek,vcodec-comp-decoder.yaml | 192 ++++++++++++++++++
1 file changed, 192 insertions(+)
create mode 100644 Documentation/devicetree/bindings/media/mediatek,vcodec-comp-decoder.yaml
diff --git a/Documentation/devicetree/bindings/media/mediatek,vcodec-comp-decoder.yaml b/Documentation/devicetree/bindings/media/mediatek,vcodec-comp-decoder.yaml
new file mode 100644
index 000000000000..2184cf7ef9e3
--- /dev/null
+++ b/Documentation/devicetree/bindings/media/mediatek,vcodec-comp-decoder.yaml
@@ -0,0 +1,192 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/iommu/mediatek,vcodec-comp-decoder.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Mediatek Video Decode Accelerator With Component
+
+maintainers:
+ - Yunfei Dong <yunfei.dong@mediatek.com>
+
+description: |+
+ Mediatek Video Decode is the video decode hardware present in Mediatek
+ SoCs which supports high resolution decoding functionalities. Required
+ master and component node.
+
+ About the Decoder Hardware Block Diagram, please check below:
+
+ +---------------------------------+------------------------------------+
+ | | |
+ | input -> lat HW -> lat buffer --|--> lat buffer -> core HW -> output |
+ | || | || |
+ +------------||-------------------+---------------------||-------------+
+ || lat thread | core thread || <master>
+ -------------||-----------------------------------------||----------------
+ || || <component>
+ \/ <----------------HW index-------------->\/
+ +------------------------------------------------------+
+ | enable/disable |
+ | clk power irq iommu port |
+ | (lat/lat soc/core0/core1) |
+ +------------------------------------------------------+
+
+ As above, <master> mean in master device, <component> mean in component device.
+ The information of each hardware will be stored in each component device. There
+ are two thread in master device: lat and core. Enable/disable the lat clk/power/irq
+ when lat hardware need to work through hardware index, core is the same.
+
+ Normally the smi common may not the same for each hardware, can't combine all
+ hardware in one node, or leading to iommu fault when access dram data.
+
+properties:
+ compatible:
+ - enum:
+ - mediatek,mt8192-vcodec-dec # for lat hardware
+ - mediatek,mtk-vcodec-lat # for core hardware
+ - mediatek,mtk-vcodec-core
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ clocks:
+ maxItems: 5
+
+ clock-names:
+ items:
+ - const: vdec-sel
+ - const: vdec-soc-vdec
+ - const: vdec-soc-lat
+ - const: vdec-vdec
+ - const: vdec-top
+
+ power-domains:
+ maxItems: 1
+
+ iommus:
+ minItems: 1
+ maxItems: 32
+ description: |
+ List of the hardware port in respective IOMMU block for current Socs.
+ Refer to bindings/iommu/mediatek,iommu.yaml.
+
+ dma-ranges:
+ maxItems: 1
+ description: |
+ Describes the physical address space of IOMMU maps to memory.
+
+ mediatek,scp:
+ $ref: /schemas/types.yaml#/definitions/phandle
+ maxItems: 1
+ description:
+ Describes point to scp.
+
+required:
+ - compatible
+ - reg
+ - iommus
+ - dma-ranges
+
+allOf:
+ - if: #master node
+ properties:
+ compatible:
+ contains:
+ enum:
+ - mediatek,mt8192-vcodec-dec # for lat hardware
+
+ then:
+ required:
+ - mediatek,scp
+
+ - if: #component node
+ properties:
+ compatible:
+ contains:
+ enum:
+ - mediatek,mtk-vcodec-lat # for core hardware
+ - mediatek,mtk-vcodec-core
+
+ then:
+ required:
+ - interrupts
+ - clocks
+ - clock-names
+ - assigned-clocks
+ - assigned-clock-parents
+ - power-domains
+
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/memory/mt8192-larb-port.h>
+ #include <dt-bindings/interrupt-controller/irq.h>
+ #include <dt-bindings/clock/mt8192-clk.h>
+ #include <dt-bindings/power/mt8192-power.h>
+
+ vcodec_dec: vcodec_dec@16000000 {
+ compatible = "mediatek,mt8192-vcodec-dec";
+ reg = <0 0x16000000 0 0x1000>; /* VDEC_SYS */
+ mediatek,scp = <&scp>;
+ iommus = <&iommu0 M4U_PORT_L4_VDEC_MC_EXT>;
+ dma-ranges = <0x1 0x0 0x0 0x40000000 0x0 0xfff00000>;
+ };
+
+ vcodec_lat: vcodec_lat@0x16010000 {
+ compatible = "mediatek,mtk-vcodec-lat";
+ reg = <0 0x16010000 0 0x800>; /* VDEC_MISC */
+ interrupts = <GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH 0>;
+ iommus = <&iommu0 M4U_PORT_L5_VDEC_LAT0_VLD_EXT>,
+ <&iommu0 M4U_PORT_L5_VDEC_LAT0_VLD2_EXT>,
+ <&iommu0 M4U_PORT_L5_VDEC_LAT0_AVC_MV_EXT>,
+ <&iommu0 M4U_PORT_L5_VDEC_LAT0_PRED_RD_EXT>,
+ <&iommu0 M4U_PORT_L5_VDEC_LAT0_TILE_EXT>,
+ <&iommu0 M4U_PORT_L5_VDEC_LAT0_WDMA_EXT>,
+ <&iommu0 M4U_PORT_L5_VDEC_LAT0_RG_CTRL_DMA_EXT>,
+ <&iommu0 M4U_PORT_L5_VDEC_UFO_ENC_EXT>;
+ dma-ranges = <0x1 0x0 0x0 0x40000000 0x0 0xfff00000>;
+ clocks = <&topckgen CLK_TOP_VDEC_SEL>,
+ <&vdecsys_soc CLK_VDEC_SOC_VDEC>,
+ <&vdecsys_soc CLK_VDEC_SOC_LAT>,
+ <&vdecsys_soc CLK_VDEC_SOC_LARB1>,
+ <&topckgen CLK_TOP_MAINPLL_D4>;
+ clock-names = "vdec-sel", "vdec-soc-vdec", "vdec-soc-lat",
+ "vdec-vdec", "vdec-top";
+ assigned-clocks = <&topckgen CLK_TOP_VDEC_SEL>;
+ assigned-clock-parents = <&topckgen CLK_TOP_MAINPLL_D4>;
+ power-domains = <&spm MT8192_POWER_DOMAIN_VDEC>;
+ };
+
+ vcodec_core: vcodec_core@0x16025000 {
+ compatible = "mediatek,mtk-vcodec-core";
+ reg = <0 0x16025000 0 0x1000>; /* VDEC_CORE_MISC */
+ interrupts = <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH 0>;
+ iommus = <&iommu0 M4U_PORT_L4_VDEC_MC_EXT>,
+ <&iommu0 M4U_PORT_L4_VDEC_UFO_EXT>,
+ <&iommu0 M4U_PORT_L4_VDEC_PP_EXT>,
+ <&iommu0 M4U_PORT_L4_VDEC_PRED_RD_EXT>,
+ <&iommu0 M4U_PORT_L4_VDEC_PRED_WR_EXT>,
+ <&iommu0 M4U_PORT_L4_VDEC_PPWRAP_EXT>,
+ <&iommu0 M4U_PORT_L4_VDEC_TILE_EXT>,
+ <&iommu0 M4U_PORT_L4_VDEC_VLD_EXT>,
+ <&iommu0 M4U_PORT_L4_VDEC_VLD2_EXT>,
+ <&iommu0 M4U_PORT_L4_VDEC_AVC_MV_EXT>,
+ <&iommu0 M4U_PORT_L4_VDEC_RG_CTRL_DMA_EXT>;
+ dma-ranges = <0x1 0x0 0x0 0x40000000 0x0 0xfff00000>;
+ clocks = <&topckgen CLK_TOP_VDEC_SEL>,
+ <&vdecsys CLK_VDEC_VDEC>,
+ <&vdecsys CLK_VDEC_LAT>,
+ <&vdecsys CLK_VDEC_LARB1>,
+ <&topckgen CLK_TOP_MAINPLL_D4>;
+ clock-names = "vdec-sel", "vdec-soc-vdec", "vdec-soc-lat",
+ "vdec-vdec", "vdec-top";
+ assigned-clocks = <&topckgen CLK_TOP_VDEC_SEL>;
+ assigned-clock-parents = <&topckgen CLK_TOP_MAINPLL_D4>;
+ power-domains = <&spm MT8192_POWER_DOMAIN_VDEC2>;
+ };
--
2.25.1
next prev parent reply other threads:[~2021-09-01 8:32 UTC|newest]
Thread overview: 35+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-09-01 8:32 [PATCH v6, 00/15] Using component framework to support multi hardware decode Yunfei Dong
2021-09-01 8:32 ` [PATCH v6, 01/15] media: mtk-vcodec: Get numbers of register bases from DT Yunfei Dong
2021-09-01 8:32 ` [PATCH v6, 02/15] media: mtk-vcodec: Align vcodec wake up interrupt interface Yunfei Dong
2021-09-01 8:32 ` [PATCH v6, 03/15] media: mtk-vcodec: Refactor vcodec pm interface Yunfei Dong
2021-09-01 8:32 ` [PATCH v6, 04/15] media: mtk-vcodec: Use component framework to manage each hardware information Yunfei Dong
2021-09-01 8:32 ` [PATCH v6, 05/15] dt-bindings: media: mtk-vcodec: Separate video encoder and decoder dt-bindings Yunfei Dong
2021-09-01 8:32 ` [PATCH v6, 06/15] media: mtk-vcodec: Use pure single core for MT8183 Yunfei Dong
2021-09-01 8:32 ` [PATCH v6, 07/15] media: mtk-vcodec: Add irq interface for multi hardware Yunfei Dong
2021-09-01 8:32 ` [PATCH v6, 08/15] media: mtk-vcodec: Add msg queue feature for lat and core architecture Yunfei Dong
2021-09-01 8:32 ` [PATCH v6, 09/15] media: mtk-vcodec: Generalize power and clock on/off interfaces Yunfei Dong
2021-09-01 8:32 ` [PATCH v6, 10/15] media: mtk-vcodec: Add new interface to lock different hardware Yunfei Dong
2021-09-01 8:32 ` [PATCH v6, 11/15] media: mtk-vcodec: Add core thread Yunfei Dong
2021-09-01 8:32 ` [PATCH v6, 12/15] media: mtk-vcodec: Support 34bits dma address for vdec Yunfei Dong
2021-10-07 11:37 ` Benjamin Gaignard
2021-10-11 5:42 ` yunfei.dong
2021-09-01 8:32 ` Yunfei Dong [this message]
2021-09-02 12:03 ` [PATCH v6, 13/15] dt-bindings: media: mtk-vcodec: Adds decoder dt-bindings for mt8192 Rob Herring
2021-09-01 8:32 ` [PATCH v6, 14/15] media: mtk-vcodec: Add core dec and dec end ipi msg Yunfei Dong
2021-09-01 8:32 ` [PATCH v6, 15/15] media: mtk-vcodec: Use codec type to separate different hardware Yunfei Dong
2021-09-01 12:17 ` Dafna Hirschfeld
2021-09-02 6:05 ` yunfei.dong
2021-09-03 12:42 ` Dafna Hirschfeld
2021-09-04 3:00 ` yunfei.dong
2021-09-02 16:30 ` [PATCH v6, 00/15] Using component framework to support multi hardware decode Ezequiel Garcia
2021-09-03 3:08 ` yunfei.dong
2021-09-14 12:16 ` yunfei.dong
2021-09-26 8:27 ` yunfei.dong
2021-09-26 14:51 ` Ezequiel Garcia
2021-09-27 17:02 ` Steve Cho
2021-10-05 6:13 ` Tomasz Figa
2021-10-13 1:17 ` yunfei.dong
2021-10-14 12:38 ` Ezequiel Garcia
2021-09-03 4:09 ` Chen-Yu Tsai
2021-09-27 16:56 ` Steve Cho
2021-09-27 17:31 ` Steve Cho
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