[PATCH v10 0/2] Add pixel format for 10 bits YUV video

[PATCH v10 0/2] Add pixel format for 10 bits YUV video

[Randy Li]

As the requirement from:
P010 fourcc format support - Was: Re: Kernel error "Unknown pixelformat
0x00000000" occurs when I start capture video

I don't know which device would support the P010, P012, P016 video pixel
format, but Rockchip would support that NV12_10LE40 and a patch for that
driver is sent before.

Randy Li (2):
  drm/fourcc: Add new P010, P016 video format
  drm/fourcc: add a 10bits fully packed variant of NV12

 drivers/gpu/drm/drm_fourcc.c  | 13 +++++++++++++
 include/uapi/drm/drm_fourcc.h | 29 +++++++++++++++++++++++++++++
 2 files changed, 42 insertions(+)

-- 
2.20.1

[PATCH v10 1/2] drm/fourcc: Add new P010, P016 video format

[Randy Li]

P010 is a planar 4:2:0 YUV with interleaved UV plane, 10 bits per
channel video format.

P012 is a planar 4:2:0 YUV 12 bits per channel

P016 is a planar 4:2:0 YUV with interleaved UV plane, 16 bits per
channel video format.

V3: Added P012 and fixed cpp for P010.
V4: format definition refined per review.
V5: Format comment block for each new pixel format.
V6: reversed Cb/Cr order in comments.
v7: reversed Cb/Cr order in comments of header files, remove
the wrong part of commit message.
V8: reversed V7 changes except commit message and rebased.
v9: used the new properties to describe those format and
rebased.

Cc: Daniel Stone <daniel@fooishbar.org>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>

Signed-off-by: Randy Li <ayaka@soulik.info>
Signed-off-by: Clint Taylor <clinton.a.taylor@intel.com>
---
 drivers/gpu/drm/drm_fourcc.c  |  9 +++++++++
 include/uapi/drm/drm_fourcc.h | 21 +++++++++++++++++++++
 2 files changed, 30 insertions(+)

diff --git a/drivers/gpu/drm/drm_fourcc.c b/drivers/gpu/drm/drm_fourcc.c
index d90ee03a84c6..ba7e19d4336c 100644
--- a/drivers/gpu/drm/drm_fourcc.c
+++ b/drivers/gpu/drm/drm_fourcc.c
@@ -238,6 +238,15 @@ const struct drm_format_info *__drm_format_info(u32 format)
 		{ .format = DRM_FORMAT_X0L2,		.depth = 0,  .num_planes = 1,
 		  .char_per_block = { 8, 0, 0 }, .block_w = { 2, 0, 0 }, .block_h = { 2, 0, 0 },
 		  .hsub = 2, .vsub = 2, .is_yuv = true },
+		{ .format = DRM_FORMAT_P010,            .depth = 0,  .num_planes = 2,
+		  .char_per_block = { 2, 4, 0 }, .block_w = { 1, 0, 0 }, .block_h = { 1, 0, 0 },
+		  .hsub = 2, .vsub = 2, .is_yuv = true},
+		{ .format = DRM_FORMAT_P012,		.depth = 0,  .num_planes = 2,
+		  .char_per_block = { 2, 4, 0 }, .block_w = { 1, 0, 0 }, .block_h = { 1, 0, 0 },
+		   .hsub = 2, .vsub = 2, .is_yuv = true},
+		{ .format = DRM_FORMAT_P016,		.depth = 0,  .num_planes = 2,
+		  .char_per_block = { 2, 4, 0 }, .block_w = { 1, 0, 0 }, .block_h = { 1, 0, 0 },
+		  .hsub = 2, .vsub = 2, .is_yuv = true},
 	};
 
 	unsigned int i;
diff --git a/include/uapi/drm/drm_fourcc.h b/include/uapi/drm/drm_fourcc.h
index 0b44260a5ee9..8dd1328bc8d6 100644
--- a/include/uapi/drm/drm_fourcc.h
+++ b/include/uapi/drm/drm_fourcc.h
@@ -195,6 +195,27 @@ extern "C" {
 #define DRM_FORMAT_NV24		fourcc_code('N', 'V', '2', '4') /* non-subsampled Cr:Cb plane */
 #define DRM_FORMAT_NV42		fourcc_code('N', 'V', '4', '2') /* non-subsampled Cb:Cr plane */
 
+/*
+ * 2 plane YCbCr MSB aligned
+ * index 0 = Y plane, [15:0] Y:x [10:6] little endian
+ * index 1 = Cr:Cb plane, [31:0] Cr:x:Cb:x [10:6:10:6] little endian
+ */
+#define DRM_FORMAT_P010		fourcc_code('P', '0', '1', '0') /* 2x2 subsampled Cr:Cb plane 10 bits per channel */
+
+/*
+ * 2 plane YCbCr MSB aligned
+ * index 0 = Y plane, [15:0] Y:x [12:4] little endian
+ * index 1 = Cr:Cb plane, [31:0] Cr:x:Cb:x [12:4:12:4] little endian
+ */
+#define DRM_FORMAT_P012		fourcc_code('P', '0', '1', '2') /* 2x2 subsampled Cr:Cb plane 12 bits per channel */
+
+/*
+ * 2 plane YCbCr MSB aligned
+ * index 0 = Y plane, [15:0] Y little endian
+ * index 1 = Cr:Cb plane, [31:0] Cr:Cb [16:16] little endian
+ */
+#define DRM_FORMAT_P016		fourcc_code('P', '0', '1', '6') /* 2x2 subsampled Cr:Cb plane 16 bits per channel */
+
 /*
  * 3 plane YCbCr
  * index 0: Y plane, [7:0] Y
-- 
2.20.1

[PATCH v10 2/2] drm/fourcc: add a 10bits fully packed variant of NV12

[Randy Li]

This pixel format is a fully packed and 10bits variant of NV12.
A luma pixel would take 10bits in memory, without any
filled bits between pixels in a stride.

Signed-off-by: Randy Li <ayaka@soulik.info>
---
 drivers/gpu/drm/drm_fourcc.c  | 4 ++++
 include/uapi/drm/drm_fourcc.h | 8 ++++++++
 2 files changed, 12 insertions(+)

diff --git a/drivers/gpu/drm/drm_fourcc.c b/drivers/gpu/drm/drm_fourcc.c
index ba7e19d4336c..16d3be8278f1 100644
--- a/drivers/gpu/drm/drm_fourcc.c
+++ b/drivers/gpu/drm/drm_fourcc.c
@@ -247,6 +247,10 @@ const struct drm_format_info *__drm_format_info(u32 format)
 		{ .format = DRM_FORMAT_P016,		.depth = 0,  .num_planes = 2,
 		  .char_per_block = { 2, 4, 0 }, .block_w = { 1, 0, 0 }, .block_h = { 1, 0, 0 },
 		  .hsub = 2, .vsub = 2, .is_yuv = true},
+		{ .format = DRM_FORMAT_NV12_10LE40,	.depth = 0,  .num_planes = 2,
+		  .char_per_block = { 5, 5, 0 }, .block_w = { 4, 2, 0 }, .block_h = { 1, 1, 0 },
+		  .hsub = 2, .vsub = 2, .is_yuv = true },
+		},
 	};
 
 	unsigned int i;
diff --git a/include/uapi/drm/drm_fourcc.h b/include/uapi/drm/drm_fourcc.h
index 8dd1328bc8d6..4985fb19b4ce 100644
--- a/include/uapi/drm/drm_fourcc.h
+++ b/include/uapi/drm/drm_fourcc.h
@@ -194,6 +194,14 @@ extern "C" {
 #define DRM_FORMAT_NV61		fourcc_code('N', 'V', '6', '1') /* 2x1 subsampled Cb:Cr plane */
 #define DRM_FORMAT_NV24		fourcc_code('N', 'V', '2', '4') /* non-subsampled Cr:Cb plane */
 #define DRM_FORMAT_NV42		fourcc_code('N', 'V', '4', '2') /* non-subsampled Cb:Cr plane */
+/*
+ * A fully packed  2 plane YCbCr
+ * Y1 0-9, Y2 10-19, Y3 20-29, Y4 20-39
+ * ....
+ * U1V1: 0-19, U2V2: 20-39
+ */
+#define DRM_FORMAT_NV12_10LE40	fourcc_code('R', 'K', '2', '0') /* 2x2 subsampled Cr:Cb plane */
+
 
 /*
  * 2 plane YCbCr MSB aligned
-- 
2.20.1

Re: [PATCH v10 1/2] drm/fourcc: Add new P010, P016 video format

[Ayan Halder]

On Thu, Jan 10, 2019 at 03:57:09AM +0800, Randy Li wrote:
> P010 is a planar 4:2:0 YUV with interleaved UV plane, 10 bits per
> channel video format.
> 
> P012 is a planar 4:2:0 YUV 12 bits per channel
> 
> P016 is a planar 4:2:0 YUV with interleaved UV plane, 16 bits per
> channel video format.
> 
> V3: Added P012 and fixed cpp for P010.
> V4: format definition refined per review.
> V5: Format comment block for each new pixel format.
> V6: reversed Cb/Cr order in comments.
> v7: reversed Cb/Cr order in comments of header files, remove
> the wrong part of commit message.
> V8: reversed V7 changes except commit message and rebased.
> v9: used the new properties to describe those format and
> rebased.
> 
> Cc: Daniel Stone <daniel@fooishbar.org>
> Cc: Ville Syrj??l?? <ville.syrjala@linux.intel.com>
> 
> Signed-off-by: Randy Li <ayaka@soulik.info>
> Signed-off-by: Clint Taylor <clinton.a.taylor@intel.com>
> ---
>  drivers/gpu/drm/drm_fourcc.c  |  9 +++++++++
>  include/uapi/drm/drm_fourcc.h | 21 +++++++++++++++++++++
>  2 files changed, 30 insertions(+)
> 
> diff --git a/drivers/gpu/drm/drm_fourcc.c b/drivers/gpu/drm/drm_fourcc.c
> index d90ee03a84c6..ba7e19d4336c 100644
> --- a/drivers/gpu/drm/drm_fourcc.c
> +++ b/drivers/gpu/drm/drm_fourcc.c
> @@ -238,6 +238,15 @@ const struct drm_format_info *__drm_format_info(u32 format)
>  		{ .format = DRM_FORMAT_X0L2,		.depth = 0,  .num_planes = 1,
>  		  .char_per_block = { 8, 0, 0 }, .block_w = { 2, 0, 0 }, .block_h = { 2, 0, 0 },
>  		  .hsub = 2, .vsub = 2, .is_yuv = true },
> +		{ .format = DRM_FORMAT_P010,            .depth = 0,  .num_planes = 2,
> +		  .char_per_block = { 2, 4, 0 }, .block_w = { 1, 0, 0 }, .block_h = { 1, 0, 0 },
> +		  .hsub = 2, .vsub = 2, .is_yuv = true},
> +		{ .format = DRM_FORMAT_P012,		.depth = 0,  .num_planes = 2,
> +		  .char_per_block = { 2, 4, 0 }, .block_w = { 1, 0, 0 }, .block_h = { 1, 0, 0 },
> +		   .hsub = 2, .vsub = 2, .is_yuv = true},
> +		{ .format = DRM_FORMAT_P016,		.depth = 0,  .num_planes = 2,
> +		  .char_per_block = { 2, 4, 0 }, .block_w = { 1, 0, 0 }, .block_h = { 1, 0, 0 },
> +		  .hsub = 2, .vsub = 2, .is_yuv = true},
>  	};
>  
>  	unsigned int i;
> diff --git a/include/uapi/drm/drm_fourcc.h b/include/uapi/drm/drm_fourcc.h
> index 0b44260a5ee9..8dd1328bc8d6 100644
> --- a/include/uapi/drm/drm_fourcc.h
> +++ b/include/uapi/drm/drm_fourcc.h
> @@ -195,6 +195,27 @@ extern "C" {
>  #define DRM_FORMAT_NV24		fourcc_code('N', 'V', '2', '4') /* non-subsampled Cr:Cb plane */
>  #define DRM_FORMAT_NV42		fourcc_code('N', 'V', '4', '2') /* non-subsampled Cb:Cr plane */
>  
> +/*
> + * 2 plane YCbCr MSB aligned
> + * index 0 = Y plane, [15:0] Y:x [10:6] little endian
> + * index 1 = Cr:Cb plane, [31:0] Cr:x:Cb:x [10:6:10:6] little endian
> + */
> +#define DRM_FORMAT_P010		fourcc_code('P', '0', '1', '0') /* 2x2 subsampled Cr:Cb plane 10 bits per channel */
> +
> +/*
> + * 2 plane YCbCr MSB aligned
> + * index 0 = Y plane, [15:0] Y:x [12:4] little endian
> + * index 1 = Cr:Cb plane, [31:0] Cr:x:Cb:x [12:4:12:4] little endian
> + */
> +#define DRM_FORMAT_P012		fourcc_code('P', '0', '1', '2') /* 2x2 subsampled Cr:Cb plane 12 bits per channel */
> +
> +/*
> + * 2 plane YCbCr MSB aligned
> + * index 0 = Y plane, [15:0] Y little endian
> + * index 1 = Cr:Cb plane, [31:0] Cr:Cb [16:16] little endian
> + */
> +#define DRM_FORMAT_P016		fourcc_code('P', '0', '1', '6') /* 2x2 subsampled Cr:Cb plane 16 bits per channel */
> +

looks good to me.
Reviewed by:- Ayan Kumar Halder <ayan.halder@arm.com>

We are using P010 format for our mali display driver. Our AFBC patch
series(https://patchwork.freedesktop.org/series/53395/) is dependent
on this patch. So, that's why I wanted to know when you are planning to
merge this. As far as I remember, Juha wanted to implement some igt
tests
(https://lists.freedesktop.org/archives/intel-gfx/2018-September/174877.html)
, so is that done now?

My apologies if I am pushing hard on this.
>  /*
>   * 3 plane YCbCr
>   * index 0: Y plane, [7:0] Y
> -- 
> 2.20.1
> 
> _______________________________________________
> dri-devel mailing list
> dri-devel@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/dri-devel

Re: [PATCH v10 1/2] drm/fourcc: Add new P010, P016 video format

[Neil Armstrong]

Hi,

On 14/01/2019 17:36, Ayan Halder wrote:
> On Thu, Jan 10, 2019 at 03:57:09AM +0800, Randy Li wrote:
>> P010 is a planar 4:2:0 YUV with interleaved UV plane, 10 bits per
>> channel video format.
>>
>> P012 is a planar 4:2:0 YUV 12 bits per channel
>>
>> P016 is a planar 4:2:0 YUV with interleaved UV plane, 16 bits per
>> channel video format.
>>
>> V3: Added P012 and fixed cpp for P010.
>> V4: format definition refined per review.
>> V5: Format comment block for each new pixel format.
>> V6: reversed Cb/Cr order in comments.
>> v7: reversed Cb/Cr order in comments of header files, remove
>> the wrong part of commit message.
>> V8: reversed V7 changes except commit message and rebased.
>> v9: used the new properties to describe those format and
>> rebased.
>>
>> Cc: Daniel Stone <daniel@fooishbar.org>
>> Cc: Ville Syrj??l?? <ville.syrjala@linux.intel.com>
>>
>> Signed-off-by: Randy Li <ayaka@soulik.info>
>> Signed-off-by: Clint Taylor <clinton.a.taylor@intel.com>
>> ---
>>  drivers/gpu/drm/drm_fourcc.c  |  9 +++++++++
>>  include/uapi/drm/drm_fourcc.h | 21 +++++++++++++++++++++
>>  2 files changed, 30 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/drm_fourcc.c b/drivers/gpu/drm/drm_fourcc.c
>> index d90ee03a84c6..ba7e19d4336c 100644
>> --- a/drivers/gpu/drm/drm_fourcc.c
>> +++ b/drivers/gpu/drm/drm_fourcc.c
>> @@ -238,6 +238,15 @@ const struct drm_format_info *__drm_format_info(u32 format)
>>  		{ .format = DRM_FORMAT_X0L2,		.depth = 0,  .num_planes = 1,
>>  		  .char_per_block = { 8, 0, 0 }, .block_w = { 2, 0, 0 }, .block_h = { 2, 0, 0 },
>>  		  .hsub = 2, .vsub = 2, .is_yuv = true },
>> +		{ .format = DRM_FORMAT_P010,            .depth = 0,  .num_planes = 2,
>> +		  .char_per_block = { 2, 4, 0 }, .block_w = { 1, 0, 0 }, .block_h = { 1, 0, 0 },
>> +		  .hsub = 2, .vsub = 2, .is_yuv = true},
>> +		{ .format = DRM_FORMAT_P012,		.depth = 0,  .num_planes = 2,
>> +		  .char_per_block = { 2, 4, 0 }, .block_w = { 1, 0, 0 }, .block_h = { 1, 0, 0 },
>> +		   .hsub = 2, .vsub = 2, .is_yuv = true},
>> +		{ .format = DRM_FORMAT_P016,		.depth = 0,  .num_planes = 2,
>> +		  .char_per_block = { 2, 4, 0 }, .block_w = { 1, 0, 0 }, .block_h = { 1, 0, 0 },
>> +		  .hsub = 2, .vsub = 2, .is_yuv = true},
>>  	};
>>  
>>  	unsigned int i;
>> diff --git a/include/uapi/drm/drm_fourcc.h b/include/uapi/drm/drm_fourcc.h
>> index 0b44260a5ee9..8dd1328bc8d6 100644
>> --- a/include/uapi/drm/drm_fourcc.h
>> +++ b/include/uapi/drm/drm_fourcc.h
>> @@ -195,6 +195,27 @@ extern "C" {
>>  #define DRM_FORMAT_NV24		fourcc_code('N', 'V', '2', '4') /* non-subsampled Cr:Cb plane */
>>  #define DRM_FORMAT_NV42		fourcc_code('N', 'V', '4', '2') /* non-subsampled Cb:Cr plane */
>>  
>> +/*
>> + * 2 plane YCbCr MSB aligned
>> + * index 0 = Y plane, [15:0] Y:x [10:6] little endian
>> + * index 1 = Cr:Cb plane, [31:0] Cr:x:Cb:x [10:6:10:6] little endian
>> + */
>> +#define DRM_FORMAT_P010		fourcc_code('P', '0', '1', '0') /* 2x2 subsampled Cr:Cb plane 10 bits per channel */
>> +
>> +/*
>> + * 2 plane YCbCr MSB aligned
>> + * index 0 = Y plane, [15:0] Y:x [12:4] little endian
>> + * index 1 = Cr:Cb plane, [31:0] Cr:x:Cb:x [12:4:12:4] little endian
>> + */
>> +#define DRM_FORMAT_P012		fourcc_code('P', '0', '1', '2') /* 2x2 subsampled Cr:Cb plane 12 bits per channel */
>> +
>> +/*
>> + * 2 plane YCbCr MSB aligned
>> + * index 0 = Y plane, [15:0] Y little endian
>> + * index 1 = Cr:Cb plane, [31:0] Cr:Cb [16:16] little endian
>> + */
>> +#define DRM_FORMAT_P016		fourcc_code('P', '0', '1', '6') /* 2x2 subsampled Cr:Cb plane 16 bits per channel */
>> +
> 
> looks good to me.
> Reviewed by:- Ayan Kumar Halder <ayan.halder@arm.com>
> 
> We are using P010 format for our mali display driver. Our AFBC patch
> series(https://patchwork.freedesktop.org/series/53395/) is dependent
> on this patch. So, that's why I wanted to know when you are planning to
> merge this. As far as I remember, Juha wanted to implement some igt
> tests
> (https://lists.freedesktop.org/archives/intel-gfx/2018-September/174877.html)
> , so is that done now?
> 
> My apologies if I am pushing hard on this.

Looks good to me aswell,

Reviewed by: Neil Armstrong <narmstrong@baylibre.com>

Seems we will also need P010 to support the Amlogic Compressed modifier to display
compressed frames from the HW decoder.

I can apply this to drm-misc-next if everyone is ok

Neil

>>  /*
>>   * 3 plane YCbCr
>>   * index 0: Y plane, [7:0] Y
>> -- 
>> 2.20.1
>>
>> _______________________________________________
>> dri-devel mailing list
>> dri-devel@lists.freedesktop.org
>> https://lists.freedesktop.org/mailman/listinfo/dri-devel
> _______________________________________________
> dri-devel mailing list
> dri-devel@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/dri-devel
> 

Re: [PATCH v10 1/2] drm/fourcc: Add new P010, P016 video format

[Daniel Vetter]

On Thu, Feb 07, 2019 at 10:44:10AM +0100, Neil Armstrong wrote:
> Hi,
> 
> On 14/01/2019 17:36, Ayan Halder wrote:
> > On Thu, Jan 10, 2019 at 03:57:09AM +0800, Randy Li wrote:
> >> P010 is a planar 4:2:0 YUV with interleaved UV plane, 10 bits per
> >> channel video format.
> >>
> >> P012 is a planar 4:2:0 YUV 12 bits per channel
> >>
> >> P016 is a planar 4:2:0 YUV with interleaved UV plane, 16 bits per
> >> channel video format.
> >>
> >> V3: Added P012 and fixed cpp for P010.
> >> V4: format definition refined per review.
> >> V5: Format comment block for each new pixel format.
> >> V6: reversed Cb/Cr order in comments.
> >> v7: reversed Cb/Cr order in comments of header files, remove
> >> the wrong part of commit message.
> >> V8: reversed V7 changes except commit message and rebased.
> >> v9: used the new properties to describe those format and
> >> rebased.
> >>
> >> Cc: Daniel Stone <daniel@fooishbar.org>
> >> Cc: Ville Syrj??l?? <ville.syrjala@linux.intel.com>
> >>
> >> Signed-off-by: Randy Li <ayaka@soulik.info>
> >> Signed-off-by: Clint Taylor <clinton.a.taylor@intel.com>
> >> ---
> >>  drivers/gpu/drm/drm_fourcc.c  |  9 +++++++++
> >>  include/uapi/drm/drm_fourcc.h | 21 +++++++++++++++++++++
> >>  2 files changed, 30 insertions(+)
> >>
> >> diff --git a/drivers/gpu/drm/drm_fourcc.c b/drivers/gpu/drm/drm_fourcc.c
> >> index d90ee03a84c6..ba7e19d4336c 100644
> >> --- a/drivers/gpu/drm/drm_fourcc.c
> >> +++ b/drivers/gpu/drm/drm_fourcc.c
> >> @@ -238,6 +238,15 @@ const struct drm_format_info *__drm_format_info(u32 format)
> >>  		{ .format = DRM_FORMAT_X0L2,		.depth = 0,  .num_planes = 1,
> >>  		  .char_per_block = { 8, 0, 0 }, .block_w = { 2, 0, 0 }, .block_h = { 2, 0, 0 },
> >>  		  .hsub = 2, .vsub = 2, .is_yuv = true },
> >> +		{ .format = DRM_FORMAT_P010,            .depth = 0,  .num_planes = 2,
> >> +		  .char_per_block = { 2, 4, 0 }, .block_w = { 1, 0, 0 }, .block_h = { 1, 0, 0 },
> >> +		  .hsub = 2, .vsub = 2, .is_yuv = true},
> >> +		{ .format = DRM_FORMAT_P012,		.depth = 0,  .num_planes = 2,
> >> +		  .char_per_block = { 2, 4, 0 }, .block_w = { 1, 0, 0 }, .block_h = { 1, 0, 0 },
> >> +		   .hsub = 2, .vsub = 2, .is_yuv = true},
> >> +		{ .format = DRM_FORMAT_P016,		.depth = 0,  .num_planes = 2,
> >> +		  .char_per_block = { 2, 4, 0 }, .block_w = { 1, 0, 0 }, .block_h = { 1, 0, 0 },
> >> +		  .hsub = 2, .vsub = 2, .is_yuv = true},
> >>  	};
> >>  
> >>  	unsigned int i;
> >> diff --git a/include/uapi/drm/drm_fourcc.h b/include/uapi/drm/drm_fourcc.h
> >> index 0b44260a5ee9..8dd1328bc8d6 100644
> >> --- a/include/uapi/drm/drm_fourcc.h
> >> +++ b/include/uapi/drm/drm_fourcc.h
> >> @@ -195,6 +195,27 @@ extern "C" {
> >>  #define DRM_FORMAT_NV24		fourcc_code('N', 'V', '2', '4') /* non-subsampled Cr:Cb plane */
> >>  #define DRM_FORMAT_NV42		fourcc_code('N', 'V', '4', '2') /* non-subsampled Cb:Cr plane */
> >>  
> >> +/*
> >> + * 2 plane YCbCr MSB aligned
> >> + * index 0 = Y plane, [15:0] Y:x [10:6] little endian
> >> + * index 1 = Cr:Cb plane, [31:0] Cr:x:Cb:x [10:6:10:6] little endian
> >> + */
> >> +#define DRM_FORMAT_P010		fourcc_code('P', '0', '1', '0') /* 2x2 subsampled Cr:Cb plane 10 bits per channel */
> >> +
> >> +/*
> >> + * 2 plane YCbCr MSB aligned
> >> + * index 0 = Y plane, [15:0] Y:x [12:4] little endian
> >> + * index 1 = Cr:Cb plane, [31:0] Cr:x:Cb:x [12:4:12:4] little endian
> >> + */
> >> +#define DRM_FORMAT_P012		fourcc_code('P', '0', '1', '2') /* 2x2 subsampled Cr:Cb plane 12 bits per channel */
> >> +
> >> +/*
> >> + * 2 plane YCbCr MSB aligned
> >> + * index 0 = Y plane, [15:0] Y little endian
> >> + * index 1 = Cr:Cb plane, [31:0] Cr:Cb [16:16] little endian
> >> + */
> >> +#define DRM_FORMAT_P016		fourcc_code('P', '0', '1', '6') /* 2x2 subsampled Cr:Cb plane 16 bits per channel */
> >> +
> > 
> > looks good to me.
> > Reviewed by:- Ayan Kumar Halder <ayan.halder@arm.com>
> > 
> > We are using P010 format for our mali display driver. Our AFBC patch
> > series(https://patchwork.freedesktop.org/series/53395/) is dependent
> > on this patch. So, that's why I wanted to know when you are planning to
> > merge this. As far as I remember, Juha wanted to implement some igt
> > tests
> > (https://lists.freedesktop.org/archives/intel-gfx/2018-September/174877.html)
> > , so is that done now?
> > 
> > My apologies if I am pushing hard on this.
> 
> Looks good to me aswell,
> 
> Reviewed by: Neil Armstrong <narmstrong@baylibre.com>
> 
> Seems we will also need P010 to support the Amlogic Compressed modifier to display
> compressed frames from the HW decoder.
> 
> I can apply this to drm-misc-next if everyone is ok

Matches what's still flaoting around by intel devs:

https://patchwork.freedesktop.org/patch/284801/

Except this one uses the new block descriptors and has much neater
comments.

Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch>

Please push to drm-misc-next asap so intel folks aren't blocked.

Thanks, Daniel

> 
> Neil
> 
> >>  /*
> >>   * 3 plane YCbCr
> >>   * index 0: Y plane, [7:0] Y
> >> -- 
> >> 2.20.1
> >>
> >> _______________________________________________
> >> dri-devel mailing list
> >> dri-devel@lists.freedesktop.org
> >> https://lists.freedesktop.org/mailman/listinfo/dri-devel
> > _______________________________________________
> > dri-devel mailing list
> > dri-devel@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/dri-devel
> > 
> 

-- 
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch

Re: [PATCH v10 1/2] drm/fourcc: Add new P010, P016 video format

[Neil Armstrong]

Le 08/02/2019 16:51, Daniel Vetter a écrit :
> On Thu, Feb 07, 2019 at 10:44:10AM +0100, Neil Armstrong wrote:
>> Hi,
>>
>> On 14/01/2019 17:36, Ayan Halder wrote:
>>> On Thu, Jan 10, 2019 at 03:57:09AM +0800, Randy Li wrote:
>>>> P010 is a planar 4:2:0 YUV with interleaved UV plane, 10 bits per
>>>> channel video format.
>>>>
>>>> P012 is a planar 4:2:0 YUV 12 bits per channel
>>>>
>>>> P016 is a planar 4:2:0 YUV with interleaved UV plane, 16 bits per
>>>> channel video format.
>>>>
>>>> V3: Added P012 and fixed cpp for P010.
>>>> V4: format definition refined per review.
>>>> V5: Format comment block for each new pixel format.
>>>> V6: reversed Cb/Cr order in comments.
>>>> v7: reversed Cb/Cr order in comments of header files, remove
>>>> the wrong part of commit message.
>>>> V8: reversed V7 changes except commit message and rebased.
>>>> v9: used the new properties to describe those format and
>>>> rebased.
>>>>
>>>> Cc: Daniel Stone <daniel@fooishbar.org>
>>>> Cc: Ville Syrj??l?? <ville.syrjala@linux.intel.com>
>>>>
>>>> Signed-off-by: Randy Li <ayaka@soulik.info>
>>>> Signed-off-by: Clint Taylor <clinton.a.taylor@intel.com>
>>>> ---
>>>>  drivers/gpu/drm/drm_fourcc.c  |  9 +++++++++
>>>>  include/uapi/drm/drm_fourcc.h | 21 +++++++++++++++++++++
>>>>  2 files changed, 30 insertions(+)
>>>>
>>>> diff --git a/drivers/gpu/drm/drm_fourcc.c b/drivers/gpu/drm/drm_fourcc.c
>>>> index d90ee03a84c6..ba7e19d4336c 100644
>>>> --- a/drivers/gpu/drm/drm_fourcc.c
>>>> +++ b/drivers/gpu/drm/drm_fourcc.c
>>>> @@ -238,6 +238,15 @@ const struct drm_format_info *__drm_format_info(u32 format)
>>>>  		{ .format = DRM_FORMAT_X0L2,		.depth = 0,  .num_planes = 1,
>>>>  		  .char_per_block = { 8, 0, 0 }, .block_w = { 2, 0, 0 }, .block_h = { 2, 0, 0 },
>>>>  		  .hsub = 2, .vsub = 2, .is_yuv = true },
>>>> +		{ .format = DRM_FORMAT_P010,            .depth = 0,  .num_planes = 2,
>>>> +		  .char_per_block = { 2, 4, 0 }, .block_w = { 1, 0, 0 }, .block_h = { 1, 0, 0 },
>>>> +		  .hsub = 2, .vsub = 2, .is_yuv = true},
>>>> +		{ .format = DRM_FORMAT_P012,		.depth = 0,  .num_planes = 2,
>>>> +		  .char_per_block = { 2, 4, 0 }, .block_w = { 1, 0, 0 }, .block_h = { 1, 0, 0 },
>>>> +		   .hsub = 2, .vsub = 2, .is_yuv = true},
>>>> +		{ .format = DRM_FORMAT_P016,		.depth = 0,  .num_planes = 2,
>>>> +		  .char_per_block = { 2, 4, 0 }, .block_w = { 1, 0, 0 }, .block_h = { 1, 0, 0 },
>>>> +		  .hsub = 2, .vsub = 2, .is_yuv = true},
>>>>  	};
>>>>  
>>>>  	unsigned int i;
>>>> diff --git a/include/uapi/drm/drm_fourcc.h b/include/uapi/drm/drm_fourcc.h
>>>> index 0b44260a5ee9..8dd1328bc8d6 100644
>>>> --- a/include/uapi/drm/drm_fourcc.h
>>>> +++ b/include/uapi/drm/drm_fourcc.h
>>>> @@ -195,6 +195,27 @@ extern "C" {
>>>>  #define DRM_FORMAT_NV24		fourcc_code('N', 'V', '2', '4') /* non-subsampled Cr:Cb plane */
>>>>  #define DRM_FORMAT_NV42		fourcc_code('N', 'V', '4', '2') /* non-subsampled Cb:Cr plane */
>>>>  
>>>> +/*
>>>> + * 2 plane YCbCr MSB aligned
>>>> + * index 0 = Y plane, [15:0] Y:x [10:6] little endian
>>>> + * index 1 = Cr:Cb plane, [31:0] Cr:x:Cb:x [10:6:10:6] little endian
>>>> + */
>>>> +#define DRM_FORMAT_P010		fourcc_code('P', '0', '1', '0') /* 2x2 subsampled Cr:Cb plane 10 bits per channel */
>>>> +
>>>> +/*
>>>> + * 2 plane YCbCr MSB aligned
>>>> + * index 0 = Y plane, [15:0] Y:x [12:4] little endian
>>>> + * index 1 = Cr:Cb plane, [31:0] Cr:x:Cb:x [12:4:12:4] little endian
>>>> + */
>>>> +#define DRM_FORMAT_P012		fourcc_code('P', '0', '1', '2') /* 2x2 subsampled Cr:Cb plane 12 bits per channel */
>>>> +
>>>> +/*
>>>> + * 2 plane YCbCr MSB aligned
>>>> + * index 0 = Y plane, [15:0] Y little endian
>>>> + * index 1 = Cr:Cb plane, [31:0] Cr:Cb [16:16] little endian
>>>> + */
>>>> +#define DRM_FORMAT_P016		fourcc_code('P', '0', '1', '6') /* 2x2 subsampled Cr:Cb plane 16 bits per channel */
>>>> +
>>>
>>> looks good to me.
>>> Reviewed by:- Ayan Kumar Halder <ayan.halder@arm.com>
>>>
>>> We are using P010 format for our mali display driver. Our AFBC patch
>>> series(https://patchwork.freedesktop.org/series/53395/) is dependent
>>> on this patch. So, that's why I wanted to know when you are planning to
>>> merge this. As far as I remember, Juha wanted to implement some igt
>>> tests
>>> (https://lists.freedesktop.org/archives/intel-gfx/2018-September/174877.html)
>>> , so is that done now?
>>>
>>> My apologies if I am pushing hard on this.
>>
>> Looks good to me aswell,
>>
>> Reviewed by: Neil Armstrong <narmstrong@baylibre.com>
>>
>> Seems we will also need P010 to support the Amlogic Compressed modifier to display
>> compressed frames from the HW decoder.
>>
>> I can apply this to drm-misc-next if everyone is ok
> 
> Matches what's still flaoting around by intel devs:
> 
> https://patchwork.freedesktop.org/patch/284801/
> 
> Except this one uses the new block descriptors and has much neater
> comments.
> 
> Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch>
> 
> Please push to drm-misc-next asap so intel folks aren't blocked.
> 
> Thanks, Daniel


Applying now, thanks !

Neil

> 
>>
>> Neil
>>
>>>>  /*
>>>>   * 3 plane YCbCr
>>>>   * index 0: Y plane, [7:0] Y
>>>> -- 
>>>> 2.20.1
>>>>
>>>> _______________________________________________
>>>> dri-devel mailing list
>>>> dri-devel@lists.freedesktop.org
>>>> https://lists.freedesktop.org/mailman/listinfo/dri-devel
>>> _______________________________________________
>>> dri-devel mailing list
>>> dri-devel@lists.freedesktop.org
>>> https://lists.freedesktop.org/mailman/listinfo/dri-devel
>>>
>>
>