From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-12.4 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH,MAILING_LIST_MULTI,NICE_REPLY_A,SIGNED_OFF_BY,SPF_HELO_NONE, SPF_PASS,USER_AGENT_SANE_1 autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id CC7AFC433FE for ; Mon, 27 Jul 2020 20:53:00 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id A807922CB1 for ; Mon, 27 Jul 2020 20:53:00 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=nvidia.com header.i=@nvidia.com header.b="rMG45YVK" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728078AbgG0Uw4 (ORCPT ); Mon, 27 Jul 2020 16:52:56 -0400 Received: from hqnvemgate26.nvidia.com ([216.228.121.65]:9194 "EHLO hqnvemgate26.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726744AbgG0Uwz (ORCPT ); Mon, 27 Jul 2020 16:52:55 -0400 Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqnvemgate26.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Mon, 27 Jul 2020 13:52:41 -0700 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate101.nvidia.com (PGP Universal service); Mon, 27 Jul 2020 13:52:55 -0700 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Mon, 27 Jul 2020 13:52:55 -0700 Received: from [10.2.168.236] (10.124.1.5) by HQMAIL107.nvidia.com (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Mon, 27 Jul 2020 20:52:54 +0000 Subject: Re: [RFC PATCH v4 04/14] i2c: tegra: Fix runtime resume to re-init VI I2C To: Dmitry Osipenko , , , , , , , CC: , , , , , , References: <1595548272-9809-1-git-send-email-skomatineni@nvidia.com> <1595548272-9809-5-git-send-email-skomatineni@nvidia.com> From: Sowjanya Komatineni Message-ID: <5d49d755-2eec-1c46-4d4c-87ec837bc5bd@nvidia.com> Date: Mon, 27 Jul 2020 13:58:37 -0700 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.10.0 MIME-Version: 1.0 In-Reply-To: X-Originating-IP: [10.124.1.5] X-ClientProxiedBy: HQMAIL111.nvidia.com (172.20.187.18) To HQMAIL107.nvidia.com (172.20.187.13) Content-Type: text/plain; charset="utf-8"; format=flowed Content-Transfer-Encoding: quoted-printable Content-Language: en-US DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1595883161; bh=UGMt8TwvCp08KuZfursHHfETCghFq1sNm6XqxSy966s=; h=X-PGP-Universal:Subject:To:CC:References:From:Message-ID:Date: User-Agent:MIME-Version:In-Reply-To:X-Originating-IP: X-ClientProxiedBy:Content-Type:Content-Transfer-Encoding: Content-Language; b=rMG45YVKb0X9dS26bZOMWmtNdQH9HjvkG7gdeI7ltFgF+RXpKPkocwPj+5mc7oh6n uUziG6tMZ6pou9YWPVP7aHDKYD0nxs2fHfxuQunw/yg1wEDSys4RTvKFMhRhe0H583 7Ues5DdGgcjBMAjn6v0Ff2i6ihEheItRk/69FYf/Hj1dgObKExY9qasdmAB6KFsqgk pr8H6tBoZ/rWKyjFYyxh8Ls0jxQTH17ZuSvxmDW22N4vtRkeRllxH4k/Fbj+/Ns1Zz 7/txNoGFEriNBdRHLGkTQyyaVvVIn5ki+yOvvyYMjowIZ1/dshww04KuhvUyWUW85Y dfow99fOdlFow== Sender: linux-media-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org On 7/26/20 4:53 PM, Dmitry Osipenko wrote: > 24.07.2020 02:51, Sowjanya Komatineni =D0=BF=D0=B8=D1=88=D0=B5=D1=82: >> VI I2C is on host1x bus and is part of VE power domain. >> >> During suspend/resume VE power domain goes through power off/on. >> >> So, controller reset followed by i2c re-initialization is required >> after the domain power up. >> >> This patch fixes it. >> >> Signed-off-by: Sowjanya Komatineni >> --- >> drivers/i2c/busses/i2c-tegra.c | 16 ++++++++++++++++ >> 1 file changed, 16 insertions(+) >> >> diff --git a/drivers/i2c/busses/i2c-tegra.c b/drivers/i2c/busses/i2c-teg= ra.c >> index 7b93c45..1bf3666 100644 >> --- a/drivers/i2c/busses/i2c-tegra.c >> +++ b/drivers/i2c/busses/i2c-tegra.c >> @@ -293,6 +293,8 @@ struct tegra_i2c_dev { >> bool is_curr_atomic_xfer; >> }; >> =20 >> +static int tegra_i2c_init(struct tegra_i2c_dev *i2c_dev, bool clk_reini= t); >> + >> static void dvc_writel(struct tegra_i2c_dev *i2c_dev, u32 val, >> unsigned long reg) >> { >> @@ -675,8 +677,22 @@ static int __maybe_unused tegra_i2c_runtime_resume(= struct device *dev) >> goto disable_slow_clk; >> } >> =20 >> + /* >> + * VI I2C device is attached to VE power domain which goes through >> + * power ON/OFF during PM runtime resume/suspend. So, controller >> + * should go through reset and need to re-initialize after power >> + * domain ON. >> + */ >> + if (i2c_dev->is_vi) { >> + ret =3D tegra_i2c_init(i2c_dev, true); >> + if (ret) >> + goto disable_div_clk; >> + } >> + >> return 0; >> =20 >> +disable_div_clk: >> + clk_disable(i2c_dev->div_clk); >> disable_slow_clk: >> clk_disable(i2c_dev->slow_clk); >> disable_fast_clk: >> > This look okay, but isn't RPM usage a bit too expensive for VI? Maybe > RPM autodelay needs to be set for the I2C driver? > > Reviewed-by: Dmitry Osipenko > Thanks Dmitry. Will look into and have separate patch for VI I2C RPM=20 auto-delay out of this series sometime next week. Regards Sowjanya