From: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
To: Maxime Ripard <maxime.ripard@free-electrons.com>
Cc: "Mauro Carvalho Chehab" <mchehab@kernel.org>,
"Mark Rutland" <mark.rutland@arm.com>,
"Rob Herring" <robh+dt@kernel.org>,
linux-media@vger.kernel.org, devicetree@vger.kernel.org,
"Cyprian Wronka" <cwronka@cadence.com>,
"Neil Webb" <neilw@cadence.com>,
"Richard Sproul" <sproul@cadence.com>,
"Alan Douglas" <adouglas@cadence.com>,
"Steve Creaney" <screaney@cadence.com>,
"Thomas Petazzoni" <thomas.petazzoni@free-electrons.com>,
"Boris Brezillon" <boris.brezillon@free-electrons.com>,
"Niklas Söderlund" <niklas.soderlund@ragnatech.se>,
"Hans Verkuil" <hans.verkuil@cisco.com>,
"Sakari Ailus" <sakari.ailus@linux.intel.com>
Subject: Re: [PATCH v2 1/2] dt-bindings: media: Add Cadence MIPI-CSI2 RX Device Tree bindings
Date: Tue, 22 Aug 2017 12:01:11 +0300 [thread overview]
Message-ID: <6400552.TlCMAsqn3H@avalon> (raw)
In-Reply-To: <20170822085320.pdxbxfv53rb75btu@flea.lan>
Hi Maxime,
On Tuesday, 22 August 2017 11:53:20 EEST Maxime Ripard wrote:
> On Mon, Aug 07, 2017 at 11:18:03PM +0300, Laurent Pinchart wrote:
> > On Thursday 20 Jul 2017 11:23:01 Maxime Ripard wrote:
> >> The Cadence MIPI-CSI2 RX controller is a CSI2RX bridge that supports up
> >> to 4 CSI-2 lanes, and can route the frames to up to 4 streams, depending
> >> on the hardware implementation.
> >>
> >> It can operate with an external D-PHY, an internal one or no D-PHY at
> >> all in some configurations.
> >
> > Without any PHY ? I'm curious, how does that work ?
>
> We're currently working on an FPGA exactly with that configuration. So
> I guess the answer would be "it doesn't on an ASIC" :)
What's connected to the input of the CSI-2 receiver ?
> >> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
> >> ---
> >>
> >> .../devicetree/bindings/media/cdns-csi2rx.txt | 87 ++++++++++++++++
> >> 1 file changed, 87 insertions(+)
> >> create mode 100644
> >> Documentation/devicetree/bindings/media/cdns-csi2rx.txt
> >>
> >> diff --git a/Documentation/devicetree/bindings/media/cdns-csi2rx.txt
> >> b/Documentation/devicetree/bindings/media/cdns-csi2rx.txt new file mode
> >> 100644
> >> index 000000000000..e08547abe885
> >> --- /dev/null
> >> +++ b/Documentation/devicetree/bindings/media/cdns-csi2rx.txt
> >> @@ -0,0 +1,87 @@
> >> +Cadence MIPI-CSI2 RX controller
> >> +===============================
> >> +
> >> +The Cadence MIPI-CSI2 RX controller is a CSI-2 bridge supporting up to
> >> 4> CSI
> >> +lanes in input, and 4 different pixel streams in output.
> >> +
> >> +Required properties:
> >> + - compatible: must be set to "cdns,csi2rx" and an SoC-specific
> >> compatible
> >> + - reg: base address and size of the memory mapped region
> >> + - clocks: phandles to the clocks driving the controller
> >> + - clock-names: must contain:
> >> + * sys_clk: main clock
> >> + * p_clk: register bank clock
> >> + * p_free_clk: free running register bank clock
> >> + * pixel_ifX_clk: pixel stream output clock, one for each stream
> >> + implemented in hardware, between 0 and 3
> >
> > Nitpicking, I would write the name is pixel_if[0-3]_clk, it took me a few
> > seconds to see that the X was a placeholder.
>
> Ok.
>
> >> + * dphy_rx_clk: D-PHY byte clock, if implemented in hardware
> >> + - phys: phandle to the external D-PHY
> >> + - phy-names: must contain dphy, if the implementation uses an
> >> + external D-PHY
> >
> > I would move the last two properties in an optional category as they're
> > effectively optional. I think you should also explain a bit more clearly
> > that the phys property must not be present if the phy-names property is
> > not present.
>
> It's not really optional. The IP has a configuration register that
> allows you to see if it's been synthesized with or without a PHY. If
> the right bit is set, that property will be mandatory, if not, it's
> useless.
Just to confirm, the PHY is a separate IP core, right ? Is the CSI-2 receiver
input interface different when used with a PHY and when used without one ?
Could a third-party PHY be used as well ? If so, would the PHY synthesis bit
be set or not ?
> Maybe it's just semantics, but to me, optional means that it can
> operate with or without it under any circumstances. It's not really
> the case here.
It'sa semantic issue, but documenting a property as required when it can be
ommitted under some circumstances seems even weirder to me :-) I understand
the optional category as "can be ommitted in certain circumstances".
> >> +
> >> +Required subnodes:
> >> + - ports: A ports node with endpoint definitions as defined in
> >> +
> >> Documentation/devicetree/bindings/media/video-interfaces.txt.
> >> The
> >> + first port subnode should be the input endpoint, the second
> >> one the
> >> + outputs
> >> +
> >> + The output port should have as many endpoints as stream supported by
> >> + the hardware implementation, between 1 and 4, their ID being the
> >> + stream output number used in the implementation.
> >
> > I don't think that's correct. The IP has four independent outputs, it
> > should have 4 output ports for a total for 5 ports. Multiple endpoints
> > per port would describe multiple connections from the same output to
> > different sinks.
>
> Ok.
--
Regards,
Laurent Pinchart
next prev parent reply other threads:[~2017-08-22 9:00 UTC|newest]
Thread overview: 17+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-07-20 9:23 [PATCH v2 0/2] media: v4l: Add support for the Cadence MIPI-CSI2 RX Maxime Ripard
2017-07-20 9:23 ` [PATCH v2 1/2] dt-bindings: media: Add Cadence MIPI-CSI2 RX Device Tree bindings Maxime Ripard
2017-07-24 19:56 ` Rob Herring
2017-08-07 19:56 ` Benoit Parrot
2017-08-07 20:18 ` Laurent Pinchart
2017-08-22 8:53 ` Maxime Ripard
2017-08-22 9:01 ` Laurent Pinchart [this message]
2017-08-22 19:25 ` Cyprian Wronka
2017-08-22 21:03 ` Laurent Pinchart
2017-08-25 14:44 ` Maxime Ripard
2017-08-25 16:34 ` Laurent Pinchart
2017-07-20 9:23 ` [PATCH v2 2/2] v4l: cadence: Add Cadence MIPI-CSI2 RX driver Maxime Ripard
2017-07-23 1:09 ` kbuild test robot
2017-08-07 19:24 ` Benoit Parrot
2017-08-25 14:03 ` Maxime Ripard
2017-08-07 20:42 ` Laurent Pinchart
2017-08-25 14:30 ` Maxime Ripard
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=6400552.TlCMAsqn3H@avalon \
--to=laurent.pinchart@ideasonboard.com \
--cc=adouglas@cadence.com \
--cc=boris.brezillon@free-electrons.com \
--cc=cwronka@cadence.com \
--cc=devicetree@vger.kernel.org \
--cc=hans.verkuil@cisco.com \
--cc=linux-media@vger.kernel.org \
--cc=mark.rutland@arm.com \
--cc=maxime.ripard@free-electrons.com \
--cc=mchehab@kernel.org \
--cc=neilw@cadence.com \
--cc=niklas.soderlund@ragnatech.se \
--cc=robh+dt@kernel.org \
--cc=sakari.ailus@linux.intel.com \
--cc=screaney@cadence.com \
--cc=sproul@cadence.com \
--cc=thomas.petazzoni@free-electrons.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).