Re: [PATCH v3 3/6] staging: media: wave5: Add the v4l2 layer

[Daniel Palmer <daniel@0x0f.com>]

Hi Dafna,

On Wed, 10 Nov 2021 at 21:09, Dafna Hirschfeld
<dafna.hirschfeld@collabora.com> wrote:
> +static int wave5_vpu_probe(struct platform_device *pdev)
> +{
> +       int ret = 0;
> +       struct vpu_device *dev;
> +       struct resource *res = NULL;
> +       const struct wave5_match_data *match_data;

.. snip ...

> +       dev->dev = &pdev->dev;
> +       dev->product_code = wave5_vdi_read_register(dev, VPU_PRODUCT_CODE_REGISTER);

You access a register here..

> +       ret = devm_clk_bulk_get_all(&pdev->dev, &dev->clks);
> +
> +       /* continue without clock, assume externally managed */
> +       if (ret < 0) {
> +               dev_warn(&pdev->dev, "unable to get clocks: %d\n", ret);
> +               ret = 0;
> +       }
> +       dev->num_clks = ret;
> +
> +       ret = clk_bulk_prepare_enable(dev->num_clks, dev->clks);
> +       if (ret) {
> +               dev_err(&pdev->dev, "failed to enable clocks: %d\n", ret);
> +               goto err_clk_prep_en;
> +       }

but only get and enable the clocks further down.

For anything that needs a clock enabled to access the register and
doesn't have it enabled when probe is called the CPU might lock up.
I found this out while trying to get this code working on another chip
that has one of these IP blocks.

Cheers,

Daniel