From: Adam Ford <aford173@gmail.com>
To: Lucas Stach <l.stach@pengutronix.de>
Cc: Martin Kepplinger <martin.kepplinger@puri.sm>,
linux-media <linux-media@vger.kernel.org>,
Adam Ford-BE <aford@beaconembedded.com>,
Chris Healy <cphealy@gmail.com>,
kernel test robot <lkp@intel.com>,
Ezequiel Garcia <ezequiel@vanguardiasur.com.ar>,
Philipp Zabel <p.zabel@pengutronix.de>,
Mauro Carvalho Chehab <mchehab@kernel.org>,
Rob Herring <robh@kernel.org>, Shawn Guo <shawnguo@kernel.org>,
Sascha Hauer <s.hauer@pengutronix.de>,
Pengutronix Kernel Team <kernel@pengutronix.de>,
Fabio Estevam <festevam@gmail.com>,
NXP Linux Team <linux-imx@nxp.com>,
Greg Kroah-Hartman <gregkh@linuxfoundation.org>,
"open list:HANTRO VPU CODEC DRIVER"
<linux-rockchip@lists.infradead.org>,
devicetree <devicetree@vger.kernel.org>,
arm-soc <linux-arm-kernel@lists.infradead.org>,
Linux Kernel Mailing List <linux-kernel@vger.kernel.org>,
"open list:STAGING SUBSYSTEM" <linux-staging@lists.linux.dev>
Subject: Re: [PATCH V4 07/11] arm64: dts: imx8mq: Enable both G1 and G2 VPU's with vpu-blk-ctrl
Date: Mon, 25 Apr 2022 10:47:04 -0500 [thread overview]
Message-ID: <CAHCN7xKEWT=-ujUD0KC9O=VUyCDSGzwbB1_dC51_k=Hx3i6+bg@mail.gmail.com> (raw)
In-Reply-To: <4b958892ba788a0e9e73a9135c305aacbe33294d.camel@pengutronix.de>
On Mon, Apr 25, 2022 at 10:34 AM Lucas Stach <l.stach@pengutronix.de> wrote:
>
> Hi Martin,
>
> Am Montag, dem 25.04.2022 um 17:22 +0200 schrieb Martin Kepplinger:
> > Am Dienstag, dem 25.01.2022 um 11:11 -0600 schrieb Adam Ford:
> > > With the Hantro G1 and G2 now setup to run independently, update
> > > the device tree to allow both to operate. This requires the
> > > vpu-blk-ctrl node to be configured. Since vpu-blk-ctrl needs
> > > certain clock enabled to handle the gating of the G1 and G2
> > > fuses, the clock-parents and clock-rates for the various VPU's
> > > to be moved into the pgc_vpu because they cannot get re-parented
> > > once enabled, and the pgc_vpu is the highest in the chain.
> > >
> > > Signed-off-by: Adam Ford <aford173@gmail.com>
> > > Reported-by: kernel test robot <lkp@intel.com>
> > > Reviewed-by: Ezequiel Garcia <ezequiel@vanguardiasur.com.ar>
> > >
> > > diff --git a/arch/arm64/boot/dts/freescale/imx8mq.dtsi
> > > b/arch/arm64/boot/dts/freescale/imx8mq.dtsi
> > > index 2df2510d0118..549b2440f55d 100644
> > > --- a/arch/arm64/boot/dts/freescale/imx8mq.dtsi
> > > +++ b/arch/arm64/boot/dts/freescale/imx8mq.dtsi
> > > @@ -737,7 +737,21 @@ pgc_gpu: power-domain@5 {
> > > pgc_vpu: power-domain@6 {
> > > #power-domain-cells =
> > > <0>;
> > > reg =
> > > <IMX8M_POWER_DOMAIN_VPU>;
> > > - clocks = <&clk
> > > IMX8MQ_CLK_VPU_DEC_ROOT>;
> > > + clocks = <&clk
> > > IMX8MQ_CLK_VPU_DEC_ROOT>,
> > > + <&clk
> > > IMX8MQ_CLK_VPU_G1_ROOT>,
> > > + <&clk
> > > IMX8MQ_CLK_VPU_G2_ROOT>;
> > > + assigned-clocks =
> > > <&clk IMX8MQ_CLK_VPU_G1>,
> > > +
> > > <&clk IMX8MQ_CLK_VPU_G2>,
> > > +
> > > <&clk IMX8MQ_CLK_VPU_BUS>,
> > > +
> > > <&clk IMX8MQ_VPU_PLL_BYPASS>;
> > > + assigned-clock-
> > > parents = <&clk IMX8MQ_VPU_PLL_OUT>,
> > > +
> > > <&clk IMX8MQ_VPU_PLL_OUT>,
> > > +
> > > <&clk IMX8MQ_SYS1_PLL_800M>,
> > > +
> > > <&clk IMX8MQ_VPU_PLL>;
> > > + assigned-clock-rates
> > > = <600000000>,
> > > +
> > > <600000000>,
> > > +
> > > <800000000>,
> > > +
> > > <0>;
> > > };
> > >
> > > pgc_disp: power-domain@7 {
> > > @@ -1457,30 +1471,31 @@ usb3_phy1: usb-phy@382f0040 {
> > > status = "disabled";
> > > };
> > >
> > > - vpu: video-codec@38300000 {
> > > - compatible = "nxp,imx8mq-vpu";
> > > - reg = <0x38300000 0x10000>,
> > > - <0x38310000 0x10000>,
> > > - <0x38320000 0x10000>;
> > > - reg-names = "g1", "g2", "ctrl";
> > > - interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
> > > - <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
> > > - interrupt-names = "g1", "g2";
> > > + vpu_g1: video-codec@38300000 {
> > > + compatible = "nxp,imx8mq-vpu-g1";
> > > + reg = <0x38300000 0x10000>;
> > > + interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
> > > + clocks = <&clk IMX8MQ_CLK_VPU_G1_ROOT>;
> > > + power-domains = <&vpu_blk_ctrl
> > > IMX8MQ_VPUBLK_PD_G1>;
> > > + };
> > > +
> > > + vpu_g2: video-codec@38310000 {
> > > + compatible = "nxp,imx8mq-vpu-g2";
> > > + reg = <0x38310000 0x10000>;
> > > + interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
> > > + clocks = <&clk IMX8MQ_CLK_VPU_G2_ROOT>;
> > > + power-domains = <&vpu_blk_ctrl
> > > IMX8MQ_VPUBLK_PD_G2>;
> > > + };
> > > +
> > > + vpu_blk_ctrl: blk-ctrl@38320000 {
> > > + compatible = "fsl,imx8mq-vpu-blk-ctrl";
> > > + reg = <0x38320000 0x100>;
> > > + power-domains = <&pgc_vpu>, <&pgc_vpu>,
> > > <&pgc_vpu>;
> > > + power-domain-names = "bus", "g1", "g2";
> > > clocks = <&clk IMX8MQ_CLK_VPU_G1_ROOT>,
> > > - <&clk IMX8MQ_CLK_VPU_G2_ROOT>,
> > > - <&clk IMX8MQ_CLK_VPU_DEC_ROOT>;
> > > - clock-names = "g1", "g2", "bus";
> > > - assigned-clocks = <&clk IMX8MQ_CLK_VPU_G1>,
> > > - <&clk IMX8MQ_CLK_VPU_G2>,
> > > - <&clk IMX8MQ_CLK_VPU_BUS>,
> > > - <&clk
> > > IMX8MQ_VPU_PLL_BYPASS>;
> > > - assigned-clock-parents = <&clk
> > > IMX8MQ_VPU_PLL_OUT>,
> > > - <&clk
> > > IMX8MQ_VPU_PLL_OUT>,
> > > - <&clk
> > > IMX8MQ_SYS1_PLL_800M>,
> > > - <&clk
> > > IMX8MQ_VPU_PLL>;
> > > - assigned-clock-rates = <600000000>,
> > > <600000000>,
> > > - <800000000>, <0>;
> > > - power-domains = <&pgc_vpu>;
> > > + <&clk IMX8MQ_CLK_VPU_G2_ROOT>;
> > > + clock-names = "g1", "g2";
> > > + #power-domain-cells = <1>;
> > > };
> > >
> > > pcie0: pcie@33800000 {
> >
> > With this update, when testing suspend to ram on imx8mq, I get:
> >
> > buck4: failed to disable: -ETIMEDOUT
> >
> > where buck4 is power-supply of pgc_vpu. And thus the transition to
> > suspend (and resuming) fails.
> >
> > Have you tested system suspend after the imx8m-blk-ctrl update on
> > imx8mq?
>
> I haven't tested system suspend, don't know if anyone else did. However
> I guess that this is just uncovering a preexisting issue in the system
> suspend sequencing, which you would also hit if the video decoders were
> active at system suspend time.
I have not tested it either.
>
> My guess is that the regulator disable fails, due to the power domains
> being disabled quite late in the suspend sequence, where i2c
> communication with the PMIC is no longer possible due to i2c being
> suspended already or something like that. Maybe you can dig in a bit on
> the actual sequence on your system and we can see how we can rework
> things to suspend the power domains at a time where communication with
> the PMIC is still possible?
In the meantime, should we mark the regulator with regulator-always-on
so it doesn't attempt to power it down? It might not be ideal,but it
might be enough to let it suspend.
adam
>
> Regards,
> Lucas
>
next prev parent reply other threads:[~2022-04-25 15:47 UTC|newest]
Thread overview: 44+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-01-25 17:11 [PATCH V4 00/11] media: hantro: imx8mq/imx8mm: Let VPU decoders get controlled by vpu-blk-ctrl Adam Ford
2022-01-25 17:11 ` [PATCH V4 01/11] arm64: dts: imx8mq-tqma8mq: Remove redundant vpu reference Adam Ford
2022-01-25 18:22 ` Lucas Stach
2022-01-25 18:57 ` Ezequiel Garcia
2022-01-26 6:42 ` (EXT) " Alexander Stein
2022-02-09 7:10 ` Shawn Guo
2022-01-25 17:11 ` [PATCH V4 02/11] dt-bindings: power: imx8mq: add defines for VPU blk-ctrl domains Adam Ford
2022-01-27 8:46 ` Hans Verkuil
2022-02-03 13:16 ` Adam Ford
2022-02-05 14:01 ` Ezequiel Garcia
2022-02-09 7:14 ` Shawn Guo
2022-01-25 17:11 ` [PATCH V4 03/11] dt-bindings: soc: add binding for i.MX8MQ VPU blk-ctrl Adam Ford
2022-02-09 7:16 ` Shawn Guo
2022-01-25 17:11 ` [PATCH V4 04/11] soc: imx: imx8m-blk-ctrl: add " Adam Ford
2022-02-09 7:19 ` Shawn Guo
2022-01-25 17:11 ` [PATCH V4 05/11] dt-bindings: media: nxp, imx8mq-vpu: Split G1 and G2 nodes Adam Ford
2022-01-25 17:11 ` [PATCH V4 06/11] media: hantro: Allow i.MX8MQ G1 and G2 to run independently Adam Ford
2022-01-25 17:11 ` [PATCH V4 07/11] arm64: dts: imx8mq: Enable both G1 and G2 VPU's with vpu-blk-ctrl Adam Ford
2022-01-25 18:20 ` Lucas Stach
2022-01-25 19:04 ` Ezequiel Garcia
2022-01-25 19:08 ` Adam Ford
2022-02-09 7:27 ` Shawn Guo
2022-04-25 15:22 ` Martin Kepplinger
2022-04-25 15:34 ` Lucas Stach
2022-04-25 15:47 ` Adam Ford [this message]
2022-04-26 10:28 ` Martin Kepplinger
2022-04-26 10:40 ` Lucas Stach
2022-04-26 7:38 ` Martin Kepplinger
2022-04-26 10:43 ` Lucas Stach
2022-04-26 12:12 ` Martin Kepplinger
2022-04-29 9:52 ` Martin Kepplinger
2022-05-23 12:00 ` Martin Kepplinger
2022-07-11 9:53 ` Martin Kepplinger
2022-07-11 12:32 ` Ezequiel Garcia
2022-01-25 17:11 ` [PATCH V4 08/11] arm64: dts: imx8mm: Fix VPU Hanging Adam Ford
2022-01-25 18:19 ` Lucas Stach
2022-02-09 7:33 ` Shawn Guo
2022-01-25 17:11 ` [PATCH V4 09/11] dt-bindings: media: nxp, imx8mq-vpu: Add support for G1 on imx8mm Adam Ford
2022-01-26 6:45 ` (EXT) " Alexander Stein
2022-02-04 23:16 ` Rob Herring
2022-01-25 17:11 ` [PATCH V4 10/11] media: hantro: Add support for i.MX8MM Hantro-G1 Adam Ford
2022-01-25 17:11 ` [PATCH V4 11/11] arm64: dts: imx8mm: Enable Hantro G1 and G2 video decoders Adam Ford
2022-01-25 18:21 ` Lucas Stach
2022-02-09 7:35 ` Shawn Guo
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